The ANTARES Neutrino Telescope was completed in May 2008 and is the first operational Neutrino Telescope in the Mediterranean Sea. The main purpose of the detector is to perform neutrino astronomy and the apparatus also offers facilities for marine and Earth sciences. This paper describes the design, the construction and the installation of the telescope in the deep sea, offshore from Toulon in France. An illustration of the detector performance is given. (C) 2011 Elsevier B.V. All rights reserved
A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.
The ATLAS IBL CollaborationDuring the shutdown of the CERN Large Hadron Collider in 2013-2014, an additional pixel layer was installed between the existing Pixel detector of the ATLAS experiment and a new, smaller radius beam pipe. The motivation for this new pixel layer, the Insertable B-Layer (IBL), was to maintain or improve the robustness and performance of the ATLAS tracking system, given the higher instantaneous and integrated luminosities realised following the shutdown. Because of the extreme radiation and collision rate environment, several new radiation-tolerant sensor and electronic technologies were utilised for this layer. This paper reports on the IBL construction and integration prior to its operation in the ATLAS detector.The ATLAS [1] general purpose detector is used for the study of proton-proton (pp) and heavy-ion collisions at the CERN Large Hadron Collider (LHC) [2]. It successfully collected data at pp collision energies of 7 and 8 TeV in the period of 2010-2012, known as Run 1. Following an LHC shutdown in 2013-2014 (LS1), it has collected data since 2015 at a pp collision energy of 13 TeV (the so-called Run 2).The ATLAS inner tracking detector (ID) [1, 3] provides charged particle tracking with high efficiency in the pseudorapidity 1 range of |η| < 2.5. With increasing radial distance from the interaction region, it consists of silicon pixel and micro-strip detectors, followed by a transition radiation tracker (TRT) detector, all surrounded by a superconducting solenoid providing a 2 T magnetic field.The original ATLAS pixel detector [4,5], referred to in this paper as the Pixel detector, was the innermost part of the ID during Run 1. It consists of three barrel layers (named the B-Layer, Layer 1 and Layer 2 with increasing radius) and three disks on each side of the interaction region, to guarantee at least three space points over the full tracking |η| range. It was designed to operate for the Phase-I period of the LHC, that is with a peak luminosity of 1 × 10 34 cm −2 s −1 and an integrated luminosity of approximately 340 fb −1 corresponding to a TID of up to 50 MRad 2 and a fluence of up to 1 × 10 15 n eq /cm 2 NIEL. However, for luminosities exceeding 2 × 10 34 cm −2 s −1 , which are now expected during the Phase-I operation, the read-out efficiency of the Pixel layers will deteriorate. This paper describes the construction and surface integration of an additional pixel layer, the Insertable B-Layer (IBL) [6], installed during the LS1 shutdown between the B-Layer and a new smaller radius beam pipe. The main motivations of the IBL were to maintain the full ID tracking performance and robustness during Phase-I operation, despite read-out bandwidth limitations of the Pixel layers (in particular the B-Layer) at the expected Phase-I peak luminosity, and accumulated radiation damage to the silicon sensors and front-end electronics. The IBL is designed to operate until the end of Phase-I, when a full tracker upgrade is planned [7] for high luminosity LHC (HL-LHC) operation from approximately ...
FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the "Insertable B-Layer" project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.
A recent analysis of the Fermi Large Area Telescope data provided evidence for a high-intensity emission of high-energy gamma rays with a E −2 spectrum from two large areas, spanning 50 • above and below the Galactic centre (the "Fermi bubbles"). A hadronic mechanism was proposed for this gamma-ray emission making the Fermi bubbles promising source candidates of high-energy neutrino emission. In this work Monte Carlo simulations regarding the detectability of high-energy neutrinos from the Fermi bubbles 4 with the future multi-km 3 neutrino telescope KM3NeT in the Mediterranean Sea are presented. Under the hypothesis that the gamma-ray emission is completely due to hadronic processes, the results indicate that neutrinos from the bubbles could be discovered in about one year of operation, for a neutrino spectrum with a cutoff at 100 TeV and a detector with about 6 km 3 of instrumented volume. The effect of a possible lower cutoff is also considered.
A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25 µm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80×336 pixels, each 50×250 µm 2 , consisting of analog and digital sections.In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL.Keywords: Pixel detector, ATLAS, upgrade, IBL, FE-I4 Scope of the project and introduction to FE-I4In these first years of operational experience with the LHC, the road to higher LHC luminosity is clearing up, allowing the detector communities to devise plans for detector upgrades.The ATLAS pixel detector will see two major phases of upgrade, phase I during the year 2016 shutdown, and phase II for the High Luminosity upgrade (HL-LHC) in 2020. For the phase I upgrade, the addition of a fourth layer to the pixel system with a smaller beam pipe is foreseen: This project is called the Insertable B-layer (IBL). For the HL-LHC upgrade, a new Inner Tracker will replace the existing one.The design of the FE-I4 has started when it was realized that the FE-I3 IC [2] presently used in the ATLAS 1 Corresponding author: barbero@physik.uni-bonn.de 2 Visitor from Laboratoire de l'Accélérateur Linéaire, Orsay, FR pixel detector [3] features an architecture which scales badly with hit rates higher than the ones expected for LHC full design luminosity. The FE-I3 is based on an architecture which requires transfer of every pixel hit down to data buffers belonging to the periphery of the IC. The pixel hit data fill these buffers until expiration of the trigger latency -typically of order 3 µs-before being transmitted for readout if triggered or, with much higher probability, erased if not triggered. The data transfer mechanism from the pixel to the periphery is time consuming and becomes highly inefficient at higher hit rates (for more information about hit recording inefficiencies at high hit rate in the current pixel FE and in FE-I4, see [4]).One of the first test chips submitted in the framework of the FE-I4 collaboration at the end of 2006 was an exploratory prototype analog array [5]. This test chip was tested in 2007 and is the basis of the present analog
A: This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5-800 Mrad. Small prototypes of 64 × 64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.
The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.
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