The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project

Zivkovic, V.; Schipper, J.; Garcia-Sciveres, M.; Mekkaoui, A.; Barbero, M.; Darbo, G.; Gnani, D.; Hemperek, T.; Menouni, M.; Fougeron, D.; Gensolen, F.; Jensen, F.; Caminada, L.; Gromov, V.; Kluit, R.; Fleury, J.; Krüger, H.; Backhaus, M.; Fang, Xiaochao; Rozanov, A.; Arutinov, D.

doi:10.1088/1748-0221/7/02/c02050

Cited by 22 publications

(16 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The FE-I4A was not intended for the final detector and the pixel matrix was non-uniform to allow performance comparisons between various analog circuit design choices. The FE-I4B chip was first fabricated in 2011 [33,34] and tailored to fully meet the IBL requirements. In addition to selecting the analog design and making the pixel matrix uniform, specific powering choices were made and data acquisition features added.…”

Section: The Fe-i4 Front-end Chipmentioning

confidence: 99%

Production and integration of the ATLAS Insertable B-Layer

et al. 2018

View full text Add to dashboard Cite

The ATLAS IBL CollaborationDuring the shutdown of the CERN Large Hadron Collider in 2013-2014, an additional pixel layer was installed between the existing Pixel detector of the ATLAS experiment and a new, smaller radius beam pipe. The motivation for this new pixel layer, the Insertable B-Layer (IBL), was to maintain or improve the robustness and performance of the ATLAS tracking system, given the higher instantaneous and integrated luminosities realised following the shutdown. Because of the extreme radiation and collision rate environment, several new radiation-tolerant sensor and electronic technologies were utilised for this layer. This paper reports on the IBL construction and integration prior to its operation in the ATLAS detector.The ATLAS [1] general purpose detector is used for the study of proton-proton (pp) and heavy-ion collisions at the CERN Large Hadron Collider (LHC) [2]. It successfully collected data at pp collision energies of 7 and 8 TeV in the period of 2010-2012, known as Run 1. Following an LHC shutdown in 2013-2014 (LS1), it has collected data since 2015 at a pp collision energy of 13 TeV (the so-called Run 2).The ATLAS inner tracking detector (ID) [1, 3] provides charged particle tracking with high efficiency in the pseudorapidity 1 range of |η| < 2.5. With increasing radial distance from the interaction region, it consists of silicon pixel and micro-strip detectors, followed by a transition radiation tracker (TRT) detector, all surrounded by a superconducting solenoid providing a 2 T magnetic field.The original ATLAS pixel detector [4,5], referred to in this paper as the Pixel detector, was the innermost part of the ID during Run 1. It consists of three barrel layers (named the B-Layer, Layer 1 and Layer 2 with increasing radius) and three disks on each side of the interaction region, to guarantee at least three space points over the full tracking |η| range. It was designed to operate for the Phase-I period of the LHC, that is with a peak luminosity of 1 × 10 34 cm −2 s −1 and an integrated luminosity of approximately 340 fb −1 corresponding to a TID of up to 50 MRad 2 and a fluence of up to 1 × 10 15 n eq /cm 2 NIEL. However, for luminosities exceeding 2 × 10 34 cm −2 s −1 , which are now expected during the Phase-I operation, the read-out efficiency of the Pixel layers will deteriorate. This paper describes the construction and surface integration of an additional pixel layer, the Insertable B-Layer (IBL) [6], installed during the LS1 shutdown between the B-Layer and a new smaller radius beam pipe. The main motivations of the IBL were to maintain the full ID tracking performance and robustness during Phase-I operation, despite read-out bandwidth limitations of the Pixel layers (in particular the B-Layer) at the expected Phase-I peak luminosity, and accumulated radiation damage to the silicon sensors and front-end electronics. The IBL is designed to operate until the end of Phase-I, when a full tracker upgrade is planned [7] for high luminosity LHC (HL-LHC) operation from approximately ...

show abstract

Section: The Fe-i4 Front-end Chipmentioning

confidence: 99%

Production and integration of the ATLAS Insertable B-Layer

et al. 2018

View full text Add to dashboard Cite

show abstract

“…The Yet Another Rapid Readout (YARR) [4] system provides simple and powerful DAQ for both current generation pixel readout chips, such as FE-I4 [5], and next generation pixel readout chips, such as RD53A. Commands are sent to, and data is read from, the pixel readout chips via a…”

Section: Yet Another Rapid Readoutmentioning

confidence: 99%

Upgrade of the YARR DAQ System for the ATLAS Phase-II Pixel Detector Readout Chip

Whallon¹,

Garcia-Sciveres²,

Sautaux³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

View full text Add to dashboard Cite

“…This 3D pixel sensor and the readout ASIC [17] were originally designed for the Insertable B Layer [18] currently being installed at the ATLAS [19] experiment at CERN, optimised for looking at high energy particles from events occurring every 25 ns. In addition to permitting studies of the beam profile, this technology offered interesting features relevant for our application as described below.…”

Section: B Second Measurements With 3d Pixel Sensormentioning

confidence: 99%