Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

Demaria, N.; Barbero, M.; Fougeron, D.; Gensolen, F.; Godiot, S.; Menouni, M.; Pangaud, P.; Rozanov, A.; Wang, A.; Bomben, M.; Calderini, G.; Crescioli, F.; Dortz, O. Le; Marchiori, G.; Dzahini, D.; Rarbi, F.; Gaglione, R.; Gonella, L.; Hemperek, T.; Huegging, F.; Karagounis, M.; Kishishita, Tetsuichi; Krueger, Hans; Rymaszewski, P.; Wermes, N.; Ciciriello, F.; Corsi, F.; Marzocca, C.; Robertis, G. De; Loddo, F.; Licciulli, F.; Andreazza, A.; Liberali, V.; Shojaii, J.; Stabile, A.; Bagatin, M.; Bisello, D.; Mattiazzo, Serena; Ding, Lili; Gerardin, Simone; Giubilato, P.; Neviani, A.; Paccagnella, A.; Vogrig, D.; Wyss, J.; Bacchetta, N.; Canio, F. De; Gaioni, L.; Nodari, B.; Manghisoni, M.; Re, V.; Traversi, G.; Comotti, D.; Ratti, L.; Vacchi, C.; Beccherle, R.; Bellazzini, R.; Magazzù, G.; Minuti, M.; Morsani, F.; Palla, F.; Poulios, S.; Fanucci, Luca; Rizzi, A.; Saponara, Sergio; Androsov, K.; Bilei, G. M.; Menichelli, M.; Conti, E.; Marconi, S.; Passeri, D.; Placidi, P.; Casa, G. Della; Mazza, G.; Rivetti, A.; Rolo, M.; Monteil, E.; Pacher, L.; Gajanana, D.; Gromov, V.; Hessey, N. P.; Kluit, R.; Zivkovic, V.; Havránek, M.; Janoska, Z.; Marčišovský, M.; Neue, G.; Tomášek, L.; Kafka, V.; Šı́cho, P.; Vrba, V.; Vila, I.; López-Morillo, E.; Aguirre, M.A.; Palomo, F.R.; Muñoz, F.; Abbaneo, D.; Christiansen, J.; Dannheim, D.; Dobos, D.; Linssen, L.; Pernegger, H.; Valerio, P.; Tehrani, N. Alipour; Bell, S.; Prydderch, M.; Thomas, S.L.; Christian, David; Fahim, Farah; Hoff, J.; Lipton, R.; Liu, T.; Zimmerman, T.; Garcia-Sciveres, M.; Gnani, D.; Mekkaoui, A.; Gorelov, I.; Hoeferkamp, M. R.; Seidel, S. C.; Toms, K.; Witt, Jeff; Grillo, A.A.; Paterno, A.

doi:10.1088/1748-0221/11/12/c12058

Cited by 22 publications

(16 citation statements)

References 10 publications

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“…Indeed, as said in the introduction, a large and complex readout chip with o(10 9 ) transistors is a huge and costly enterprise which has been addressed by the RD53 collaboration at CERN [42]. In comparison to the chips of the previous hybrid pixel generation which were column drain architectures without (1 st generation) or with (2 nd generation) a local (4-pixel) cluster efficient hit storage, this 3 rd generation contains architecture blocks with grouped logic enabling regional hit draining surrounded by synthesized logic, dubbed the 'digital sea' [43] and [44].…”

Section: Pixel Readout Chipmentioning

confidence: 99%

Pixel detectors ... where do we stand?

Wermes

2019

Nuclear Instruments and Methods in Physics Research Section A:

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Pixel detectors have been the working horse for high resolution, high rate and radiation particle tracking for the past 20 years. The field has spun off into imaging applications with equal uniqueness. Now the move is towards larger integration and fully monolithic devices with to be expected spin-off into imaging again. Many judices and prejudices that were around at times were overcome and surpassed. This paper attempts to give an account of the developments following a line of early prejudices and later insights.

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Section: Pixel Readout Chipmentioning

confidence: 99%

Pixel detectors ... where do we stand?

Wermes

2019

Nuclear Instruments and Methods in Physics Research Section A:

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“…The ratio between the eye opening and the bit period is close to 0.9. The rms jitter measured from the time interval error (TIE) 1 is…”

Section: Transmittermentioning

confidence: 99%

“…The design of the readout ASIC will face several challenges: particle fluxes, radiation dose and data bandwidth become important when moving closer to the interaction point and the pixel detectors have to work in very harsh conditions. In this context, a high data-rate differential I/O link has been designed and characterized to accommodate the RD53 requirements to send data off-chip [1]. Such differential I/O link is a well-know technique used for the chip-to-chip communication at high data rates and with a low power consumption.…”

Section: Introductionmentioning

confidence: 99%

Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications

Canio¹,

Gaioni²,

Manghisoni³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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This work is concerned with the design and characterization of an SLVS transmitter/receiver pair, to be used for I/O links in High Energy Physics applications. Core transistors with a power supply of 1.2 V have been considered in the design in order to mitigate the TID effects, due to the harsh radiation environment foreseen. The circuits have been implemented in a 65 nm CMOS technology. The prototype chip was designed and fabricated in the framework of the RD53 project and was completely characterized in the first quarter of 2016. The chip has been also irradiated with X-rays in order to evaluate the effect of the ionizing radiation on the signal integrity Topical Workshop on Electronics for Particle Physics 11

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“…The PILUP has been proposed as part of the ATLAS TDAQ read-out system for the new RD53a front-end chip [8] that will upgrade the Pixel detectors of ATLAS and CMS. Four types of data protocol have to be handled in order to set up the communication between the FELIX cards and RD53a: the GBT protocol [9] developed by CERN (output of the FELIX, with bandwidth of 4,8 Gb/s) and the Full-Mode protocol developed by the FELIX group (input of the FELIX, with bandwidth of 9,6 Gb/s), which are the protocols used by the FELIX cards, the Aurora 64b/66b protocol (output of the RD53a, with a bandwidth of 5,12 Gb/s divided in 1,28 Gb/s for each of 4 lanes) and a 160 Mb/s data lane (input of the RD53a) for the RD53a.…”

Section: Proposed Applicationmentioning

confidence: 99%