The FE-I4 pixel readout integrated circuit

Garcia-Sciveres, M.; Arutinov, D.; Barbero, M.; Beccherle, R.; Dubé, S.; Elledge, David; Fleury, J.; Fougeron, D.; Gensolen, F.; Gnani, D.; Gromov, V.; Hemperek, T.; Karagounis, M.; Kluit, R.; Kruth, A.; Mekkaoui, A.; Menouni, M.; Schipper, J.

doi:10.1016/j.nima.2010.04.101

Cited by 272 publications

(248 citation statements)

References 8 publications

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“…Several pixel flavors were tested in FE-I4A, with variations in the implementation of the pre-amplifier feedback capacity, discriminator and local latch layout. The interested reader will find more information concerning the analog pixel in [5].…”

Section: Development Of the First Full Scale Fe-i4 Prototypementioning

confidence: 99%

FE-I4 pixel readout chip and IBL module

Barbero

Hemperek²,

Zivkovic³

et al. 2012

Proceedings of the 20th Anniversary International Workshop on Vertex Detectors — PoS(Vertex 2011)

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FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the "Insertable B-Layer" project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

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Section: Development Of the First Full Scale Fe-i4 Prototypementioning

confidence: 99%

FE-I4 pixel readout chip and IBL module

Barbero

Hemperek²,

Zivkovic³

et al. 2012

Proceedings of the 20th Anniversary International Workshop on Vertex Detectors — PoS(Vertex 2011)

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“…With a lower threshold these effects will practically vanish or eventually be confined in a very small region near the corners. Recent results obtained with a low threshold of 1500 e − (using FEI4 chip for ATLAS IBL [81]) show that order of 97% detection efficiencies can be achieved with polycrystalline sensors.…”

mentioning

confidence: 99%

CMS Technical Design Report for the Pixel Detector Upgrade

Dominguez¹

2012

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The original design goal of the LHC was to operate at 1 × 10 34 cm -2 s -1 with 25 ns bunch spacing, where approximately 25 simultaneous inelastic collisions per crossing ("pile-up") occur. With the upgrade of the accelerators, the luminosity and pile-up will more than double. The current pixel detector is crucial to charged particle tracking, but was not designed to perform effectively in such collision conditions and the physics program of CMS would suffer as a result. We propose to replace the current pixel tracker with a new high efficiency and low mass detector with four barrel layers and three forward/backward disks to provide four-hit pixel coverage out to pseudorapidities of ±2.5. This new detector will meet or exceed the original design specifications in these high luminosity environments. In this report, we provide details on the design, construction and installation of the upgraded pixel detector as well as estimates of its expected performance. Cover Design S. Cittolin AcknowledgmentsWe would like to thank the technical staff from the various institutions for the design, R&D and testing of the many components of this upgrade.We also wish to thank the LHCC for their oversight and crucial advice during the development of the the pixel upgrade project. The important feedback from following CMS internal reviewers greatly helped in the development of this technical design report: D. Contardo, S. Dasu, S.C. Eno, P. Giacomelli, G. Gomez Ceballos, E. Halkiadakis, C. Hill, M. Klute, S. Lowette, M. Mannelli, S. Nahn, I. Shipsey, D. Stuart, S. Tkaczyk and J. Varela.A special thanks goes to the CMS Secretariat, in particular Anastasia Dolya, for their tireless support during all stages of the project. We also acknowledge the warm support received from the CMS management team and computing project.Finally, we dedicate this technical design report for the upgrade of the pixel detector to the memory of our two colleagues and friends:

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“…This solution has already been adopted for the selection of good 3D FE-I4s [8] sensors for the ATLAS IBL [9]. After the automatic current-voltage measurement on each FE-I4 sensor, the metal will be removed by wet etching, which does not affect the electrical characteristics of the devices.…”

Section: The Active Edge Sensor Production At Fbkmentioning

confidence: 99%

Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

Bomben

Bagolini

Boscardin

et al. 2013

Nuclear Instruments and Methods in Physics Research Section A:

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a b s t r a c tIn view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre-and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown.

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The FE-I4 pixel readout integrated circuit

Cited by 272 publications

References 8 publications

FE-I4 pixel readout chip and IBL module

FE-I4 pixel readout chip and IBL module

CMS Technical Design Report for the Pixel Detector Upgrade

Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

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