FE-I4 pixel readout chip and IBL module

Barbero, M.; Hemperek, T.; Zivkovic, V.; Kocian, M.; Menouni, M.; Lu, Y.; Große-Knetter, J.; Breugnon, P.; Fougeron, D.; Gnani, D.; Dubé, S.; Garcia-Sciveres, M.; Kruth, A.; Backhaus, M.; Rozanov, A.; Krüger, Hans; Gensolen, F.; Weingarten, J.; Wermes, N.; Mekkaoui, A.; Arutinov, D.; Jensen, F.; Beccherle, R.; Fang, Xiaochao; Caminada, L.; Fleury, J.; Kluit, R.; Schipper, J.; Darbo, G.; Gromov, V.

doi:10.22323/1.137.0038

Cited by 24 publications

(26 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…40 wafers of 60 chips were produced and the performance of the chip was evaluated in detailed studies. Very promising results were obtained and the functionality of all basic building blocks could be confirmed [9]. Furthermore, FE-I4A based modules with planar as well as 3D silicon sensors were built.…”

Section: Fe-i4 Designmentioning

confidence: 83%

Atlas Fei4 Asic

Caminada¹

2013

Proceedings of the 21st International Workshop on Vertex Detectors — PoS(Vertex 2012)

View full text Add to dashboard Cite

The ATLAS FE-I4 ASIC is a novel pixel detector readout chip designed in a CMOS 130 nm feature size process. The chip is able to cope with high hit rate and withstand the harsh radiation environment in close proximity to the interaction point at LHC. FE-I4 will find its first application with ATLAS IBL, an additional innermost pixel layer scheduled for installation in 2013, but is also suited for the intermediate radii pixel layers for future upgrades. In this paper, the modular design concept of FE-I4 is introduced and its readout architecture, analog performance and radiation hardness are discussed. After the successful development of the first full-scale prototype version of the chip in 2010, the production version for IBL (FE-I4B) has recently become available. Here, we review the main design choices for FE-I4B and present first testing results.

show abstract

Section: Fe-i4 Designmentioning

confidence: 83%

Atlas Fei4 Asic

Caminada¹

2013

Proceedings of the 21st International Workshop on Vertex Detectors — PoS(Vertex 2012)

View full text Add to dashboard Cite

show abstract

“…[12]). Again, the tests showed a very good performance of the chip, so that this chip version will be installed in the IBL [13]. The FE-I4 chip holds an active area of 16.8 mm × 20 mm and contains the readout circuitry for 26880 hybrid pixels arranged in 80 columns and 336 rows.…”

Section: Detector Front-end Electronicsmentioning

confidence: 99%

“…Fourth, as the PDR included the memory, the active fraction of the IC is improved. More information and performance measurements can be found in [13].…”

Section: Detector Front-end Electronicsmentioning

confidence: 99%

Overview of the Insertable B-Layer (IBL) project of the ATLAS experiment at the large hadron collider at CERN

Flick

2013

2013 3rd International Conference on Advancements in Nuclear Instrumentation, Measurement Methods and Their Applications (ANIMM

View full text Add to dashboard Cite

The ATLAS experiment will upgrade its Pixel Detector with the installation of a new pixel layer in 2013/14. The new subdetector, named Insertable B-Layer (IBL), will be installed between the existing Pixel Detector and a new smaller diameter beam-pipe at a radius of 33 mm. To cope with the high radiation and hit occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed and are currently under investigation and production for the IBL. Furthermore, the physics performance should be improved through the reduction of pixel size whereas targeting for a low material budget, pushing for a new mechanical support using lightweight staves and a CO2 based cooling system. An overview of the IBL project, the results of beam tests on different sensor technologies, testing of pre-series staves made before going into production in order to qualify the assembly procedure, the loaded module electrical integrity, and the read-out chain will be presented.

show abstract

“…Fig. 1 shows as an example a possible 3D version of one pixel cell of the FE-I4 [1], the new generation ATLAS pixel Front-End (FE) chip. This could be a 3D stack of two tiers, containing the analog and digital part of the chip.…”

Section: Introductionmentioning

confidence: 99%

Experience with 3D integration technologies in the framework of the ATLAS pixel detector upgrade for the HL-LHC

Aruntinov

Barbero

Hemperek

et al. 2013

Nuclear Instruments and Methods in Physics Research Section A:

View full text Add to dashboard Cite

a b s t r a c t 3D technologies are investigated for the upgrade of the ATLAS pixel detector at the HL-LHC. R&D focuses on both, IC design in 3D, as well as on post-processing 3D technologies such as Through Silicon Via (TSV). The first one uses a so-called via first technology, featuring the insertion of small aspect ratio TSV at the pixel level. As discussed in the paper, this technology can still present technical challenges for the industrial partners. The second one consists of etching the TSV via last. This technology is investigated to enable 4-side abuttable module concepts, using today's pixel detector technology. Both approaches are presented in this paper and results from first available prototypes are discussed.

show abstract

FE-I4 pixel readout chip and IBL module

Cited by 24 publications

References 9 publications

Atlas Fei4 Asic

Atlas Fei4 Asic

Overview of the Insertable B-Layer (IBL) project of the ATLAS experiment at the large hadron collider at CERN

Experience with 3D integration technologies in the framework of the ATLAS pixel detector upgrade for the HL-LHC

Contact Info

Product

Resources

About