CMS Technical Design Report for the Pixel Detector Upgrade

Dominguez, A.

doi:10.2172/1151650

Cited by 80 publications

(74 citation statements)

References 29 publications

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“…In order to understand changes in the electrical properties of the ROCs for Layers 2, 3 and 4, a few single chip modules (a sandwich of a single ROC and bump-bonded silicon sensor) have been exposed to different doses with 24 MeV protons in the irradiation facility of the Karlsruhe Institute for Technology. As it was described in the CMS TDR for the pixel detector upgrade [1], during the running period up to LS3 the LHC is expected to deliver about 500 fb −1 .…”

Section: Irradiation Studiesmentioning

confidence: 93%

“…Both effects allow to reliably operate a ROC at lower thresholds. After 200÷250 fb −1 , due to radiation damage of the silicon sensor the amount of a collected charge per minimum ionizing particle decreases from 24 ke − down to 12 ke − [1]. Hence a possibility to operate ROCs at low threshold will increase the longevity of the detector.…”

Section: Upgrade Pixel Read Out Chip For Layers 2 3 Andmentioning

confidence: 99%

“…To this end, a new ROC has been designed to be used in the modules of Layers 2, 3 and 4 and another special ROC is being designed for the modules in Layer 1. A completely new pixel detector will be built [1] with a planned installation in CMS during the extended winter shutdown in 2016/17. The ROCs for the upgraded pixel detector are an evolution of the present architecture.…”

Section: Introductionmentioning

confidence: 99%

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The CMS Pixel Readout Chip for the Phase 1 Upgrade

Hits¹,

Starodumov

2015

J. Inst.

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The present CMS pixel Read Out Chip (ROC) was designed for operation at a bunch spacing of 25 ns and to be efficient up to the nominal instantaneous luminosity of 10 34 cm −2 s −1 . Based on the excellent LHC performance to date and the upgrade plans for the accelerators, it is anticipated that the instantaneous luminosity could reach 2 × 10 34 cm −2 s −1 before the Long Shutdown 2 (LS2) in 2018, and well above this by the LS3 in 2022. That is why a new ROC has been designed and why a completely new pixel detector will be built with a planned installation in CMS during an extended winter shutdown in 2016/17. The ROC for the upgraded pixel detector is an evolution of the present architecture. It will be manufactured in the same 250 nm CMOS process. The core of the architecture is maintained, with enhancement in performance in three main areas: readout protocol, reduced data loss and enhanced analog performance. The main features of the new CMS pixel ROC are presented together with measured performance of the chip. ABSTRACT: The present CMS pixel Read Out Chip (ROC) was designed for operation at a bunch spacing of 25 ns and to be efficient up to the nominal instantaneous luminosity of 10 34 cm −2 s −1 . Based on the excellent LHC performance to date and the upgrade plans for the accelerators, it is anticipated that the instantaneous luminosity could reach 2 × 10 34 cm −2 s −1 before the Long Shutdown 2 (LS2) in 2018, and well above this by the LS3 in 2022. That is why a new ROC has been designed and why a completely new pixel detector will be built with a planned installation in CMS during an extended winter shutdown in 2016/17. The ROC for the upgraded pixel detector is an evolution of the present architecture. It will be manufactured in the same 250 nm CMOS process. The core of the architecture is maintained, with enhancement in performance in three main areas: readout protocol, reduced data loss and enhanced analog performance. The main features of the new CMS pixel ROC are presented together with measured performance of the chip.

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Section: Irradiation Studiesmentioning

confidence: 93%

Section: Upgrade Pixel Read Out Chip For Layers 2 3 Andmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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The CMS Pixel Readout Chip for the Phase 1 Upgrade

Hits¹,

Starodumov

2015

J. Inst.

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“…To see if we can actually use the Micron AP for HEP track pattern recognition, we developed a proof-of-principle application where we implement a hypothetical electron track confirmation trigger using a toy tracking detector that roughly approximates the actual 4-layer Phase-1 CMS pixel detector [5]. EM clusters found in the calorimeter are projected back into the interaction region to see if there are pixel detector hits consistent with those from a charged particle track pointing towards the cluster.…”

Section: Proof-of-principle Application With a Toy Cms Detectormentioning

confidence: 99%

Investigating the Micron Automata Processor for HEP Pattern Recognition Applications

Wang¹,

Green²,

Liu³

2017

Proceedings of the 25th International Workshop on Vertex Detectors — PoS(Vertex 2016)

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The Micron Automata Processor is a dedicated pattern matching engine that is based on a nonVon Neumann processor architecture, and was designed primarily to satisfy the growing needs of high-speed text-based pattern search applications. We investigate its suitability for HEP pattern recognition applications, using a sample track-confirmation trigger to demonstrate a proof-ofprinciple. We compare its performance, in this sample application, with that of other processor architectures, namely a general purpose CPU and an FPGA-based implementation using contentaddressable memories.

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“…To this end a new detector with improved components and additional features will be installed [4]. A fourth layer in the barrel and an additional disk on each side will provide more measuring points and thus an improved tracking performance.…”

Section: The Phase I Upgrade Of the Cms Pixel Detectormentioning

confidence: 99%

Radiation tolerance of the readout chip for the Phase I upgrade of the CMS pixel detector

et al. 2016

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For the Phase I upgrade of the CMS pixel detector a new digital readout chip (ROC) has been developed. An important part of the design verification are irradiation studies to ensure sufficient radiation tolerance. The paper summarizes results of the irradiation studies on the final ROC design for the detector layers 2 − 4. Samples have been irradiated with 23 MeV protons to accumulate the expected lifetime dose of 0.5 MGy and up to 1.1 MGy to project the performance of the ROC for layer 1 of the detector. It could be shown that the design is sufficiently radiation tolerant and that all performance parameters stay within their specifications. Additionally, very high doses of up to 4.2 MGy have been tested to explore the limits of the current chip design on 250 nm CMOS technology. The study confirmed that samples irradiated up to the highest dose could be successfully operated with test pulses. ABSTRACT: For the Phase I upgrade of the CMS pixel detector a new digital readout chip (ROC) has been developed. An important part of the design verification are irradiation studies to ensure sufficient radiation tolerance. The paper summarizes results of the irradiation studies on the final ROC design for the detector layers 2 − 4. Samples have been irradiated with 23 MeV protons to accumulate the expected lifetime dose of 0.5 MGy and up to 1.1 MGy to project the performance of the ROC for layer 1 of the detector. It could be shown that the design is sufficiently radiation tolerant and that all performance parameters stay within their specifications. Additionally, very high doses of up to 4.2 MGy have been tested to explore the limits of the current chip design on 250 nm CMOS technology. The study confirmed that samples irradiated up to the highest dose could be successfully operated with test pulses.

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CMS Technical Design Report for the Pixel Detector Upgrade

Cited by 80 publications

References 29 publications

The CMS Pixel Readout Chip for the Phase 1 Upgrade

The CMS Pixel Readout Chip for the Phase 1 Upgrade

Investigating the Micron Automata Processor for HEP Pattern Recognition Applications

Radiation tolerance of the readout chip for the Phase I upgrade of the CMS pixel detector

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