Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

Barbero, M.; Arutinov, D.; Beccherle, R.; Darbo, G.; Dubé, S.; Elledge, David; Fleury, J.; Fougeron, D.; Garcia-Sciveres, M.; Gensolen, F.; Gnani, D.; Gromov, V.; Jensen, F.; Hemperek, T.; Karagounis, M.; Kluit, R.; Kruth, A.; Mekkaoui, A.; Menouni, M.; Schipper, J.; Wermes, N.; Zivkovic, V.

doi:10.1016/j.nima.2010.11.131

Cited by 22 publications

(18 citation statements)

References 13 publications

(9 reference statements)

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“…Each FE-I4 pixel contains a free running clock-based amplification stage with adjustable shaping, followed by a discriminator with an independently adjustable threshold. The chip keeps track of the time stamp for each discriminator as well as the 4-bit Time over Threshold (ToT) 8 . Information from all firing discriminators is kept in the chip for a latency interval programmable up to 255 LHC clock cycles of 25 ns, and is retrieved if a trigger is supplied within this latency.…”

Section: The Fe-i4 Front-end Chipmentioning

confidence: 99%

Production and integration of the ATLAS Insertable B-Layer

et al. 2018

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The ATLAS IBL CollaborationDuring the shutdown of the CERN Large Hadron Collider in 2013-2014, an additional pixel layer was installed between the existing Pixel detector of the ATLAS experiment and a new, smaller radius beam pipe. The motivation for this new pixel layer, the Insertable B-Layer (IBL), was to maintain or improve the robustness and performance of the ATLAS tracking system, given the higher instantaneous and integrated luminosities realised following the shutdown. Because of the extreme radiation and collision rate environment, several new radiation-tolerant sensor and electronic technologies were utilised for this layer. This paper reports on the IBL construction and integration prior to its operation in the ATLAS detector.The ATLAS [1] general purpose detector is used for the study of proton-proton (pp) and heavy-ion collisions at the CERN Large Hadron Collider (LHC) [2]. It successfully collected data at pp collision energies of 7 and 8 TeV in the period of 2010-2012, known as Run 1. Following an LHC shutdown in 2013-2014 (LS1), it has collected data since 2015 at a pp collision energy of 13 TeV (the so-called Run 2).The ATLAS inner tracking detector (ID) [1, 3] provides charged particle tracking with high efficiency in the pseudorapidity 1 range of |η| < 2.5. With increasing radial distance from the interaction region, it consists of silicon pixel and micro-strip detectors, followed by a transition radiation tracker (TRT) detector, all surrounded by a superconducting solenoid providing a 2 T magnetic field.The original ATLAS pixel detector [4,5], referred to in this paper as the Pixel detector, was the innermost part of the ID during Run 1. It consists of three barrel layers (named the B-Layer, Layer 1 and Layer 2 with increasing radius) and three disks on each side of the interaction region, to guarantee at least three space points over the full tracking |η| range. It was designed to operate for the Phase-I period of the LHC, that is with a peak luminosity of 1 × 10 34 cm −2 s −1 and an integrated luminosity of approximately 340 fb −1 corresponding to a TID of up to 50 MRad 2 and a fluence of up to 1 × 10 15 n eq /cm 2 NIEL. However, for luminosities exceeding 2 × 10 34 cm −2 s −1 , which are now expected during the Phase-I operation, the read-out efficiency of the Pixel layers will deteriorate. This paper describes the construction and surface integration of an additional pixel layer, the Insertable B-Layer (IBL) [6], installed during the LS1 shutdown between the B-Layer and a new smaller radius beam pipe. The main motivations of the IBL were to maintain the full ID tracking performance and robustness during Phase-I operation, despite read-out bandwidth limitations of the Pixel layers (in particular the B-Layer) at the expected Phase-I peak luminosity, and accumulated radiation damage to the silicon sensors and front-end electronics. The IBL is designed to operate until the end of Phase-I, when a full tracker upgrade is planned [7] for high luminosity LHC (HL-LHC) operation from approximately ...

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Section: The Fe-i4 Front-end Chipmentioning

confidence: 99%

Production and integration of the ATLAS Insertable B-Layer

et al. 2018

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“…Integrated in the periphery is also a DC-DC divide by 2 charge pump converter. A more detailed description of FE-I4A's periphery is given in [8].…”

Section: Fe-i4a Peripherymentioning

confidence: 99%

FE-I4 pixel readout chip and IBL module

Barbero

Hemperek²,

Zivkovic³

et al. 2012

Proceedings of the 20th Anniversary International Workshop on Vertex Detectors — PoS(Vertex 2011)

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FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the "Insertable B-Layer" project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

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“…The first submission (FE-I4A) was received back in fall 2010 [14]. Intensive tests showed a very good behavior of the chip.…”

Section: Detector Front-end Electronicsmentioning

confidence: 99%

Overview of the Insertable B-Layer (IBL) project of the ATLAS experiment at the large hadron collider at CERN

Flick

2013

2013 3rd International Conference on Advancements in Nuclear Instrumentation, Measurement Methods and Their Applications (ANIMM

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The ATLAS experiment will upgrade its Pixel Detector with the installation of a new pixel layer in 2013/14. The new subdetector, named Insertable B-Layer (IBL), will be installed between the existing Pixel Detector and a new smaller diameter beam-pipe at a radius of 33 mm. To cope with the high radiation and hit occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed and are currently under investigation and production for the IBL. Furthermore, the physics performance should be improved through the reduction of pixel size whereas targeting for a low material budget, pushing for a new mechanical support using lightweight staves and a CO2 based cooling system. An overview of the IBL project, the results of beam tests on different sensor technologies, testing of pre-series staves made before going into production in order to qualify the assembly procedure, the loaded module electrical integrity, and the read-out chain will be presented.

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Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

Cited by 22 publications

References 13 publications

Production and integration of the ATLAS Insertable B-Layer

Production and integration of the ATLAS Insertable B-Layer

FE-I4 pixel readout chip and IBL module

Overview of the Insertable B-Layer (IBL) project of the ATLAS experiment at the large hadron collider at CERN

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