As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits.

As the minimum dimensions of complementary metal oxide semiconductor (CMOS) transistors shrink down to 90 nm and below, some physical obstacles have been observed which prevent rigidly this miniaturization. For example, high transistor leakage currents lead to an important increase of the ‘idle’ power consumption of CMOS memory arrays. Many nanodevices are therefore the subject of research and development to help CMOS technology continue to downscale by Moore's law. Among them, the magnetic tunnel junction (MTJ) is one of the most promising candidates, because its non‐volatility offers the possibility to power off the chip to greatly reduce the ‘idle’ energy dissipation of conventional CMOS circuits. Moreover, its resistance value property (several kΩ), compatible with CMOS transistor conductivity, allows its states to be sensed easily with CMOS circuits. The novel spin transfer torque (STT) writing approach, which has been recently introduced and developed, reduces significantly the switching energy and data disturbance when compared with the conventional MTJ writing approach. It makes the MTJ technology much more suitable than other nanodevices for commercial applications. In this paper, hybrid STT‐based MTJ (spin‐MTJ)/CMOS logic circuits and some design techniques are proposed based on STMicroelectronics 90 nm CMOS technology and the published Hitachi spin‐MTJ technology. A first prototype has been simulated and evaluated. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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The general purpose of spin-electronics is to take advantage of the spin of the electrons in addition to their electrical charge to conceive innovative electronic components. These components combine magnetic materials which are used as spin-polarizer or analyzer together with semiconductors or insulators. SPINTEC Laboratory works on the development of these components and their integration in innovative hybrid CMOS/magnetic architectures. We study in particular the use of Magnetic Tunnel Junctions (MTJ) for the design of Magnetic Random Access Memories (MRAM), Magnetic FPGA (MFPGA) and non-reprogrammable logical devices (transceivers, adders, decoders). The design of these hybrid architectures requires to develop electrical equivalent models of the magnetic elementary components (magnetic tunnel junctions, spin-valves, Hall crosses) compatible with SPICE-like simulators. Complete simulations of the hybrid devices are performed before experimental realization and testing.

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As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance and non-volatility. The integration of MRAM in FPGA allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, easily realize the dynamical reconfiguration and multicontext configuration. However, the conventional MRAM technology based on Field Induced Magnetic Switching (FIMS) writing approach consumes very high power and large circuit surface, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Thermally Assisted Switching (TAS) based MRAM is then evaluated to address these issues and some design techniques for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology, some chip characteristic results have been calculated to demonstrate the expected performance of TAS-MRAM based FPGA logic circuits.

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