A non-volatile flip-flop in magnetic FPGA chip

Zhao, Weisheng; Belhaire, E.; Javerliac, V.; Chappert, C.; Diény, B.

doi:10.1109/dtis.2006.1708702

Cited by 40 publications

(33 citation statements)

References 9 publications

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“…It was firstly proposed in 2006 and the idea is to replace one of the master or slave parts by the circuit similar to a non-volatile configuration point [38]. In 2008, NEC presented the first prototype based on 0.15μm hybrid process and high performance up to 3.5 GHz was shown.…”

Section: Magnetic Flip-flop (Mff)mentioning

confidence: 99%

“…As the switching of MRAM cell consumes always much more than a SRAM, two special techniques have been developed to reduce the switching power of MFF (see Equation 10), which should be operating at a very high frequency fswitch (>MHz) [38,39]. One is checking point: MFF stores the intermediate data in MTJs with a manageable slow frequency (e.g.…”

Section: Magnetic Flip-flop (Mff)mentioning

confidence: 99%

“…Since current MRAMs cannot perform as fast as SRAMs, a hybrid MRAM/SRAM cell was proposed in [38]. These registers keep their information stored as an electrical Another approach is to provide the operating systems with an infrastructure for context switching.…”

Section: Mram Applications For Processor Coresmentioning

confidence: 99%

“…Currently, this feature is available either by providing several register windows or by saving and restoring the register contents in the cache memory. MRAM-based multi-context registers [38] can be used to save multiple contexts locally, avoiding transactions with the cache hierarchy.…”

Section: Mram Applications For Processor Coresmentioning

confidence: 99%

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High Performance SoC Design Using Magnetic Logic and Memory

Zhao

Torres

Cargnini

et al. 2012

VLSI-SoC: Advanced Research for Systems on Chip

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Abstract.As the technolody node shrinks down to 90nm and below, high standby power becomes one of the major critical issues for CMOS highspeed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies, such as FRAM, MRAM, PCRAM and RRAM, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy integration on top of CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both physical and architectural points of view.

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Section: Magnetic Flip-flop (Mff)mentioning

confidence: 99%

Section: Magnetic Flip-flop (Mff)mentioning

confidence: 99%

Section: Mram Applications For Processor Coresmentioning

confidence: 99%

Section: Mram Applications For Processor Coresmentioning

confidence: 99%

See 2 more Smart Citations

High Performance SoC Design Using Magnetic Logic and Memory

Zhao

Torres

Cargnini

et al. 2012

VLSI-SoC: Advanced Research for Systems on Chip

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show abstract

“…Further models have also been suggested where the logical state of the GMR unit is manipulated using FIMS [11][12][13][14][15]. Similar programmable models based on spin valve magneto-logic devices are also known in literature [16][17][18]. These later models, based on CIMS, involve additional spin-valve elements that together form a single logical unit, or more than one current carrying plate capable of generating fields in orthogonal directions.…”

Section: Introductionmentioning

confidence: 99%

Spin-Transfer-Torque Driven Magneto-Logic Gates Using Nano Spin-Valve Pillars

Sanid¹,

Murugesh²

2012

Jpn. J. Appl. Phys.

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We propose model magneto-logic NOR and NAND gates using a spin valve pillar, wherein the logical operation is induced by spin-polarized currents which also form the logical inputs. The operation is facilitated by the simultaneous presence of a constant controlling magnetic field. The same spin-valve assembly can also be used as a magnetic memory unit. We identify regions in the parameter space of the system where the logical operations can be effectively performed. The proposed gates retain the non-volatility of a magnetic random access memory (MRAM). We verify the functioning of the gate by numerically simulating its dynamics, governed by the appropriate Landau-Lifshitz-Gilbert equation with the spin-transfer torque term. The flipping time for the logical states is estimated to be within nano seconds. * murugesh@iist.ac.in 2

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An MTJ‐based non‐volatile flip‐flop for high‐performance SoC

Jung

Kim

Ryu

et al. 2012

Circuit Theory & Apps

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SUMMARYThe conventional magnetic tunneling junction (MTJ)-based non-volatile D flip-flop (NVDFF) has a slow D-Q delay and a tradeoff between its D-Q delay and its sensing current. In addition, a sufficient write current cannot be obtained with the core device, since two MTJs exist in the write path and a write current degradation problem occurs due to the precharge transistors. The proposed MTJ-based non-volatile semidynamic flip-flop (NVSDFF) has a semidynamic structure that ensures a fast D-Q delay and separates the sensing circuit from the D-Q signal path to reduce the sensing current without affecting the D-Q delay. The proposed NVSDFF also provides a sufficient write current by merely using the core device, since only one MTJ exists in the write path. In addition, the head switch, which is added to remove the write current degradation problem, further reduces the sensing current. Thus, the proposed NVSDFF has a higher read disturbance margin than the previous NVDFF with an IO device. The HSPICE simulation results with the industry-compatible 45 nm model parameter show that the D-Q delay in the proposed NVSDFF is 50.5% of that of the previous NVDFF with an IO device, and the sensing current, 32.3%. In the proposed NVSDFF, the read disturbance margin is 15.9% larger than in the previous NVDFF with an IO device, and the area is 17.8% smaller.

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A non-volatile flip-flop in magnetic FPGA chip

Cited by 40 publications

References 9 publications

High Performance SoC Design Using Magnetic Logic and Memory

High Performance SoC Design Using Magnetic Logic and Memory

Spin-Transfer-Torque Driven Magneto-Logic Gates Using Nano Spin-Valve Pillars

An MTJ‐based non‐volatile flip‐flop for high‐performance SoC

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