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A 2 in. active‐matrix light‐emitting diode (AMLED) display by integration of the micro‐LED onto the oxide thin‐film transistor (TFT) backplane using flip chip bonding is reported. A blue‐emitting micro‐LED (µ‐LED) with a size of 90 × 50 µm2 is fabricated on the GaN epi grown on a sapphire substrate. The amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) TFT on glass exhibiting the mobility of 18.4 cm2 V−1 s−1, turn‐on voltage (V ON) of 0.2 V, and subthreshold swing 0.25 V dec−1, is used for LED backplane. A two TFT and one capacitance pixel structure is utilized for driving 128 × 384 AMLED with 120 Hz frame rate. The laser lift‐off process with flip‐chip bond allows the transfer of the µ‐LED chips with 49 152 pixels onto the TFT backplane, demonstrating a 2 in. AMLED display with a good gray scale image. The current efficiency of µ‐LED is found to be 12.9 Cd A−1 at the luminance of 630 Cd m−2. Therefore, a‐IGZO TFT backplane can be used for µ‐LED displays.

Highly robust poly-Si thin-film transistor (TFT) on polyimide (PI) substrate using blue laser annealing (BLA) of amorphous silicon (a-Si) for lateral crystallization is demonstrated. Its foldability is compared with the conventional excimer laser annealing (ELA) poly-Si TFT on PI used for foldable displays exhibiting field-effect mobility of 85 cm 2 (V s) À1 . The BLA poly-Si TFT on PI exhibits the field-effect mobility, threshold voltage (V TH ), and subthreshold swing of 153 cm 2 (V s) À1 , À2.7 V, and 0.2 V dec À1 , respectively. Most important finding is the excellent foldability of BLA TFT compared with the ELA poly-Si TFTs on PI substrates. The V TH shift of BLA poly-Si TFT is %0.1 V, which is much smaller than that (%2 V) of ELA TFT on PI upon 30 000 cycle folding. The defects are generated at the grain boundary region of ELA poly-Si during folding. However, BLA poly-Si has no protrusion in the poly-Si channel and thus no defect generation during folding. This leads to excellent foldability of BLA poly-Si on PI substrate.

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The low-temperature polysilicon oxide (LTPO) complementary metal-oxidesemiconductor (CMOS) thin-film transistors (TFTs) is fabricated by p-type lowtemperature polysilicon (LTPS) TFT and n-type amorphous indium-gallium-zinc oxide (a-IGZO) TFT using coplanar structure. A double-stack SiO 2 layer deposited by high temperature first and then low-temperature process is used as a gate insulator for LTPS TFT, leading to reduce the number of photomask steps. The p-channel LTPS TFT of the fabricated LTPO circuits exhibits the field-effect mobility (μ FE) and threshold voltage (V TH) of 89.9 cm 2 (V s) À1 and À5.5 V, respectively. However, the a-IGZO TFT exhibits the μ FE of 22.5 cm 2 (V s) À1 and V TH of À1.3 V. Both the LTPS TFT and a-IGZO TFT show excellent bias stability (ΔV TH of <0.1 V) and zero hysteresis voltage, which reveals the excellent interface between gate insulator and semiconductor. The LTPO CMOS inverter exhibits a gain of 264.5 V V À1 and a high noise margin of 4.29 V, and a low noise margin of 3.69 V at V DD of 8 V. Therefore, the LTPO TFT technology developed in this work can be a promising candidate for low cost, large-area manufacturing of display, and TFT electronics.