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The purpose of this study was to evaluate the ability of an aperture complexity metric for volumetric-modulated arc therapy (VMAT) plans to predict plan delivery accuracy. We developed a complexity analysis tool as a plug-in script to Varian’s Eclipse treatment planning system. This script reports the modulation of plans, arcs, and individual control points for VMAT plans using a previously developed complexity metric. The calculated complexities are compared to that of 649 VMAT plans previously treated at our institution from 2013 to mid-2015. We used the VMAT quality assurance (QA) results from the 649 treated plans, plus 62 plans that failed pretreatment QA, to validate the ability of the complexity metric to predict plan deliverability. We used a receiver operating characteristic (ROC) analysis to determine an appropriate complexity threshold value above which a plan should be considered for reoptimization before it moves further through our planning workflow. The average complexity metric for the 649 treated plans analyzed with the script was 0.132 mm−1 with a standard deviation of 0.036 mm−1. We found that when using a threshold complexity value of 0.180 mm−1, the true positive rate for correctly identifying plans that failed QA was 44%, and the false-positive rate was 7%. Used clinically with this threshold, the script can identify overly modulated plans and thus prevent a significant portion of QA failures. Reducing VMAT plan complexity has a number of important clinical benefits, including improving plan deliverability and reducing treatment time. Use of the complexity metric during both the planning and QA processes can reduce the number of QA failures and improve the quality of VMAT plans used for treatment.

Die-stacked DRAM is a technology that will soon be integrated in high-performance systems. Recent studies have focused on hardware caching techniques to make use of the stacked memory, but these approaches require complex changes to the processor and also cannot leverage the stacked memory to increase the system's overall memory capacity. In this work, we explore the challenges of exposing the stacked DRAM as part of the system's physical address space. This non-uniform access memory (NUMA) styled approach greatly simplifies the hardware and increases the physical memory capacity of the system, but pushes the burden of managing the heterogeneous memory architecture (HMA) to the software layers. We first explore simple (and somewhat impractical) schemes to manage the HMA, and then refine the mechanisms to address a variety of hardware and software implementation challenges. In the end, we present an HMA approach with low hardware and software impact that can dynamically tune itself to different application scenarios, achieving performance even better than the (impractical-to-implement) baseline approaches.

Flash is a widely used storage device that provides high density and low power, appealing properties for general purpose computing. Today, its usual application is in portable special purpose devices such as MP3 players. In this paper we examine its use in the server domaina more general purpose environment. Aggressive process scaling and the use of multi-level cells continues to improve density ahead of Moore's Law predictions, making Flash even more attractive as a general purpose memory solution. Unfortunately, reliability limits the use of Flash. To seriously consider Flash in the server domain, architectural support must exist to address this concern. This paper first shows how Flash can be used in today's server platforms as a disk cache. It then proposes two improvements. The first improves performance and reliability by splitting Flash based disk caches into separate read and write regions. The second improves reliability by employing a programmable Flash memory controller. It can change the error code strength (number of correctable bits) and the number of bits that a memory cell can store (cell density) according to the demands of the application. Our studies show that Flash reduces overall power consumed by the system memory and hard disk drive up to 3 times while maintaining performance. We also show that Flash lifetime can be improved by a factor of 20 when using a programmable Flash memory controller, if some performance degradation (below 5%) is acceptable.

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