PicoServer: Using 3D Stacking Technology to Build Energy Efficient Servers

Kgil, Taeho; Roberts, David; Mudge, Trevor

doi:10.1007/978-1-4419-0784-4_9

Cited by 29 publications

(30 citation statements)

References 32 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The product of the number of signal contacts is multiplied by the maximum rate for each type of I/O, and then divided by the maximum number of transistors (in units of a million) that can be placed on such a chip. 13 Thus if a core consumed a million transistors, regardless of feature size, this chart then gives insight into how much exclusive offchip bandwidth might be available to just that core at each point in time.…”

Section: Available Off-chip Bandwidth Per Unit Logicmentioning

confidence: 99%

“…Black et al [1] studied two forms of die stacking: placing cache chips on top of a conventional microprocessor, and splitting such a microprocessor into two die. Ghosh and Lee [7] and Kgil et al [13] studied microarchitectures that use 3D stacking to reduce energy costs. Loh [18] discussed re-architecting DRAM die that would stack above a conventional processor core in ways that increase the bandwidth and memory level parallelism of the memory as seen by the processor.…”

Section: Emerging 3d Architecturesmentioning

confidence: 99%

See 1 more Smart Citation

Yearly update : exascale projections for 2013.

Kogge

Resnick²

2013

View full text Add to dashboard Cite

The HPC architectures of today are significantly different for a decade ago, with high odds that further changes will occur on the road to Exascale. This paper discusses the "perfect storm" in technology that produced this change, the classes of architectures we are dealing with, and probable trends in how they will evolve. These properties and trends are then evaluated in terms of what it likely means to future Exascale systems and applications. 3This page intentionally left blank.

show abstract

Section: Available Off-chip Bandwidth Per Unit Logicmentioning

confidence: 99%

Section: Emerging 3d Architecturesmentioning

confidence: 99%

Yearly update : exascale projections for 2013.

Kogge

Resnick²

2013

View full text Add to dashboard Cite

show abstract

“…One of the first solutions implementing multiple memory layers on top of processors was presented by Kgil [15], modeling a web server as a CMP built of four DRAM layers stacked on top of a processing die hosting up to eight parallel cores.…”

Section: Related Workmentioning

confidence: 99%

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Beanato

Giovannini

Cevrero

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…In this paper, we use this structure as one of the comparison points and demonstrate that our proposed architecture is superior. In [28], a CMP design with stacked memory layers is proposed. The authors show that the L2 cache can be removed due to the availability of wide low-latency inter-layer buses between the processing core layer and DRAM layers, and the area saved from this can be recycled for additional cores.…”

Section: D Architecturesmentioning

confidence: 99%

“…Currently, there exists no systematic effort at exploring the interconnect architecture for 3D chips. Recently, researchers have started examining some tradeoffs, such as the influence of bandwidth variation of inter-layer interconnects between processor and memory subsystems [28], and combining vertical interconnects with an NoC fabric for chip multiprocessor caches [32].…”

Section: Introductionmentioning

confidence: 99%

A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]

Nicopoulos

Narayanan

Das

2009

Lecture Notes in Electrical Engineering

View full text Add to dashboard Cite

Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities and burgeoning die sizes in multi-core architectures. Partitioning a larger die into smaller segments and then stacking them in a 3D fashion can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible compared to intra-wafer distances. This attribute substantially reduces global wiring length in 3D chips. The work in this paper integrates the increasingly popular idea of packet-based Networks-on-Chip (NoC) into a 3D setting. While NoCs have been studied extensively in the 2D realm, the microarchitectural ramifications of moving into the third dimension have yet to be fully explored. This paper presents a detailed exploration of inter-strata communication architectures in 3D NoCs. Three design options are investigated; a simple busbased inter-wafer connection, a hop-by-hop standard 3D design, and a full 3D crossbar implementation. In this context, we propose a novel partially-connected 3D crossbar structure, called the 3D Dimensionally-Decomposed (DimDe) Router, which provides a good tradeoff between circuit complexity and performance benefits. Simulation results using (a) a stand-alone cycle-accurate 3D NoC simulator running synthetic workloads, and (b) a hybrid 3D NoC/cache simulation environment running real commercial and scientific benchmarks, indicate that the proposed DimDe design provides latency and throughput improvements of over 20% on average over the other 3D architectures, while remaining within 5% of the full 3D crossbar performance. Furthermore, based on synthesized hardware implementations in 90 nm technology, the DimDe architecture outperforms all other designs − including the full 3D crossbar − by an average of 26% in terms of the Energy-Delay Product (EDP).

show abstract

PicoServer: Using 3D Stacking Technology to Build Energy Efficient Servers

Cited by 29 publications

References 32 publications

Yearly update : exascale projections for 2013.

Yearly update : exascale projections for 2013.

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]

Contact Info

Product

Resources

About