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Victor V. Zyuban When it comes to performance, modern computer design has become a well structured art which starts with instruction sets that maximize opportunities for concurrency, follows through with fast organizational techniques such as pipelining and super scalar execution, and ends with clever macro and circuit designs that are based on inherently fast CMOS fabrication technologies. When it comes to low power, however, exactly the opposite is true. Current techniques start with lowering supply voltages and making process changes to minimize capacitance, followed by some relatively simple techniques for minimizing power for particular logic macros, and then utilizing relatively ad hoc techniques, such as 'sleep modes', at higher levels. This work attempts to reverse this by bringing the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization of high-performance microprocessors at the microarchitecture level. In particular, our work explores solutions to the problem that do not compromise performance. First, major targets for power reduction are identified within microarchitecture, where power is heavily consumed, or will be heavily consumed in next-generation processors. This involves developing energy models for structures where power grows with increasing issue width, such as Register File, Issue Window, Memory Disambiguation Unit, etc. Then, a multicluster microar-CHAPTER 6: IMPLEMENTATION OF THE ENERGY-EFFICIENT MULTI-CLUSTER ARCHITECTURE .

Processing-in-memory (PIM) chips that integrate processor logic into memory devices offer a new opportunity for bridging the growing gap between processor and memory speeds, especially for applications with high memory-bandwidth requirements. The Data-IntensiVe Architecture (DIVA) system combines PIM memories with one or more external host processors and a PIM-to-PIM interconnect. DIVA increases memory bandwidth through two mechanisms: (1) performing selected computation in memory, reducing the quantity of data transferred across the processor-memory interface; and (2) providing communication mechanisms called parcels for moving both data and computation throughout memory, further bypassing the processor-memory bus. DIVA uniquely supports acceleration of important irregular applications, including sparse-matrix and pointer-based computations. In this paper, we focus on several aspects of DIVA designed to effectively support such computations at very high performance levels: (1) the memory model and parcel definitions; (2) the PIM-to-PIM interconnect; and, (3) requirements for the processor-to-memory interface. We demonstrate the potential of PIMbased architectures in accelerating the performance of three irregular computations, sparse conjugate gradient, a natural-join database operation and an object-oriented database query.

The quantum cellular automata (QCA) is currently being investigated as an alternative to CMOS VLSI. While some simple logical circuits and devices have been studied, little if any work has been done in considering the architecture for systems of QCA devices. This work discusses the progress of one of the ÿrst such e orts. Namely, the design of data ow components for a simple microprocessor being designed exclusively in QCA are discussed. Problems associated with initial designs and enumerated solutions to these problems (usually stemming from oorplanning techniques) are explained. Finally, areas of future research direction for circuit design in QCA are presented. Copyright ? 2001 John Wiley & Sons, Ltd.

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