Inherently lower-power high-performance superscalar architectures

Abstract

Victor V. Zyuban When it comes to performance, modern computer design has become a well structured art which starts with instruction sets that maximize opportunities for concurrency, follows through with fast organizational techniques such as pipelining and super scalar execution, and ends with clever macro and circuit designs that are based on inherently fast CMOS fabrication technologies. When it comes to low power, however, exactly the opposite is true. Current techniques start with lowering supply voltages and making process changes to minimize capacitance, followed by some relatively simple techniques for minimizing power for particular logic macros, and then utilizing relatively ad hoc techniques, such as 'sleep modes', at higher levels. This work attempts to reverse this by bringing the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization of high-performance microprocessors at the microarchitecture level. In particular, our work explores solutions to the problem that do not compromise performance. First, major targets for power reduction are identified within microarchitecture, where power is heavily consumed, or will be heavily consumed in next-generation processors. This involves developing energy models for structures where power grows with increasing issue width, such as Register File, Issue Window, Memory Disambiguation Unit, etc. Then, a multicluster microar-CHAPTER 6: IMPLEMENTATION OF THE ENERGY-EFFICIENT MULTI-CLUSTER ARCHITECTURE .

Modulo scheduling for a fully-distributed clustered VLIW architecture

“…Since we are concerned with differences among alternative schedulers, we prefer not to include the effect of cycle time in our metric, to isolate the effect of the schedulers. A study of the impact of clustering on cycle time can be found elsewhere [ 191 as well as on energy consumption [26], which is another important factor that can be reduced through clustering.…”

Energy-aware compilation and hardware design for VLIW embedded systems

“…In high performance processors research work can be found that is devoted to defining mechanisms that decrease the energy of multiported register files. Regarding the hardware approaches to the problem, Zyuban and Kogge (1998) have studied the complexity of shared register files and Seznec et al (2002) and Zyuban and Kogge (2001) have proposed distributed schemes and techniques to split the global microarchitecture into distributed clusters with subsets of the register file and functional units. Similarly, trying to reduce the complexity of the register files, Cruz et al (2000) have studied the benefits of multilevel register file organisations.…”

Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures

“…In high-performance processors research devoted to defining mechanisms that decrease the energy of multiported register files can be found. Regarding the hardware approaches to the problem, Zyuban and Kogge [31] have studied the complexity of shared register files and Scznec et al [32] and Zyuban and Kogge [33] have proposed distributed schemes and techniques to split the global microarchitecture into distributed clusters with subsets of the register file and functional units. Similarly, other works like [34] have studied the benefits of multilevel register file organizations.…”