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This paper presents an in-depth study, implementation, and validation of Fast Fourier Transform Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to get faster real time in broadband digital receivers. To support the signal processing designer when implementing this kind of systems on FPGA platforms we have developed a design space exploration tool for FFT architectures.

Abstract-In this work we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation.

Abstract-SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.

Abstract-Current nanometer technologies suffer within-die parameter uncertainties, varying workload conditions, aging, and temperature effects that cause a serious reduction on yield and performance. In this scenario, monitoring, calibration, and dynamic adaptation become essential, demanding systems with a collection of multi purpose monitors and exposing the need for light-weight monitoring networks. This paper presents a new monitoring network paradigm able to perform an early prioritization of the information. This is achieved by the introduction of a new hierarchy level, the threshing level. Targeting it, we propose a time-domain signaling scheme over a single-wire that minimizes the network switching activity as well as the routing requirements. To valídate our approach, we make a thorough analysis of the architectural trade-offs and expose two complete monitoring systems that suppose an área improvement of 40% and a power reduction of three orders of magnitude compared to previous works.

Abstract-Since the memristor was first built in 2008 at HP Labs, no end of devices and models have been presented. Also, new applications appear frequently. However, the integration of the device at the circuit level is not straightforward, because available models are still immature and/or suppose high computational loads, making their simulation long and cumbersome. This study assists circuit/systems designers in the integration of memristors in their applications, while aiding model developers in the validation of their proposals. We introduce the use of a memristor application framework to support the work of both the model developer and the circuit designer. First, the framework includes a library with the best-known memristor models, being easily extensible with upcoming models. Systematic modifications have been applied to these models to provide better convergence and significant simulations speedups. Second, a quick device simulator allows the study of the response of the models under different scenarios, helping the designer with the stimuli and operation time selection. Third, fine tuning of the device including parameters variations and threshold determination is also supported. Finally, SPICE/Spectre subcircuit generation is provided to ease the integration of the devices in application circuits. The framework provides the designer with total control overconvergence, computational load, and the evolution of system variables, overcoming usual problems in the integration of memristive devices.

He obtained his BS in physics from University of Science and Technology of China and his PhD in electrical engineering from Massachusetts Institute of Technology. He was an Enrico Fermi Fellow at Argonne National Laboratory from 2018 to 2019. His research interests include nanoelectronics, nanophotonics, and emerging materials for energy harvesting, sensing, and communication applications. Dr. Jesú s Grajal received his PhD in electrical engineering from Universidad Polité cnica de Madrid (UPM) in 1998. Since 2017, he has been a Full Professor with the Signals, Systems, and Radiocommunications Department at UPM. His current research interests include semiconductor device modeling and high-frequency circuit and system design. Dr. Marisa Ló pez-Vallejo received a PhD in electronic engineering from Universidad Polité cnica de Madrid (UPM) in 1999. She was with Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA as a Member of the Technical Staff. Since 2016, she has been a Full Professor with the Electronic Engineering Department at UPM. Her major interests are in the area of low power, PVTaware design, computer-aided diagnostic methods and tools, emerging memories, and application-specific high-performance programmable architectures.

Most power reduction techniques have focused on gating the clock to unused functional units to minimize static power consumption, while system level optimizations have been used to deal with dynamic power consumption. Once these techniques are applied, register file power consumption becomes a dominant factor in the processor. This paper proposes a power-aware reconfiguration mechanism in the register file driven by a compiler. Optimal usage of the register file in terms of size is achieved and unused registers are put into a lowpower state. Total energy consumption in the register file is reduced by 65% with no appreciable performance penalty for MiBench benchmarks on an embedded processor. The effect of reconfiguration granularity on energy savings is also analyzed, and the compiler approach to optimize energy results is presented.