A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations

Kogge, Peter M.; Stone, Harold S.

doi:10.1109/tc.1973.5009159

Cited by 1,016 publications

(379 citation statements)

References 2 publications

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“…The parallel prefix adder is implemented with Kogge-Stone technique [19] where radix-4 and sparsity-4 options are used [20,21]. The entire 64-bit Kogge-Stone adder block is designed with full custom design approach (Fig.…”

Section: Implemented Blockmentioning

confidence: 99%

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Baltacı

Leblebici

2017

Integration

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A B S T R A C TThermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40 nm node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations and hotspot locations are studied. The influence of local power density on peak temperature is examined. It is shown that high power density devices have significant influence on peak temperature in FDSOI. It is found that some group of devices that perform the same function are the most prominent heat generators. A modification on the design of these devices is proposed which decreases the hotspot temperatures significantly.

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Section: Implemented Blockmentioning

confidence: 99%

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Baltacı

Leblebici

2017

Integration

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“…Among various adders, the KoggeStone carry-look-ahead adder (CLA) is well known as the fastest adder. It is based on a parallel prefix algorithm for carry computation [4]. While in the ripple carry adder, each adder bit must wait for a carry output from less significant bit, in the CLA, all the carry outputs are calculated simultaneously.…”

Section: Digit-serial Addermentioning

confidence: 99%

“…To increase the clock frequency, feedback paths of the carry signals are broken into several small paths. Our digit-serial adder is based on the Kogge-Stone CLA [4]. Fig.…”

Section: Algorithm Of Digit-serial Additionmentioning

confidence: 99%

Design of fast digit-serial adders using SFQ logic circuits

Park

Yamanashi

Yoshikawa

et al. 2009

IEICE Electron. Express

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Abstract:We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digitserial adder using the SRL 2.5 kA/cm 2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ±15% at 25 GHz. Its maximum operation frequency was 30 GHz. Keywords: SFQ circuit, superconducting device, josephson junction, digit-serial adder, adder, carry look-ahead adder Classification: Superconducting electronics

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“…If one (G, P ) does not output to any other component, the component and its input connections are removed. In this example, (G, P ) [4,1] , (G, P ) [4,2] and (G, P ) [3,1] are removed first. As a result, (G, P ) [3,2] and (G, P ) [2,1] are now unnecessary.…”

Section: Algorithm 1 Prefix Adder Constructionmentioning

confidence: 99%

An algorithmic approach for generic parallel adders

Liu¹,

Zhou²,

Zhu³

et al. 2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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Abstract-Binary addition is the most fundamental and frequently used operation. A well-designed adder should be fast and satisfy the application requirements. We propose an algorithmic approach to generate an irregular parallel-prefix adder, which has minimal delay for a given profile of input signals. It can cover different topologies such as ripple-carry, carry-skip and carry-select adders. Compared with Kogge-Stone and BrentKung adders, the results of the proposed approach have the smallest output delay. I. INTRODUCTIONDatapath module is essential for high quality ASIC design, and may dominate the whole system performance. Arithmetic components, such as adders, multipliers and shifters, are considered as basic cells to a construct datapath. Design of arithmetic components should be high performance and satisfy the application requirements. Binary addition is the most fundamental and frequently used operation in computing systems. To speed up binary addition, many different architectures have been proposed over the years.The ripple-carry adder has the minimal area, but is quite slow. The carry-skip adder [1] can speed up binary addition with a small hardware overhead. The carry-select adder [2] accelerates binary addition further, but suffers from large hardware penalty. The carry-lookahead adder [3] [4] comes with prefix computation. It has O(log n) time and O(n log n) area. Brent-Kung parallel prefix adder and Kogge-Stone parallel prefix adder are two classical regular prefix computation structures, which reach lower bound of area and lower bound of time [5] respectively.

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A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations

Cited by 1,016 publications

References 2 publications

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Design of fast digit-serial adders using SFQ logic circuits

An algorithmic approach for generic parallel adders

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