Ultra-low-power adiabatic quantum flux parametron (QFP) logic is investigated since it has the potential to reduce the bit energy per operation to the order of the thermal energy. In this approach, nonhysteretic QFPs are operated slowly to prevent nonadiabatic energy dissipation occurring during switching events. The designed adiabatic QFP gate is estimated to have a dynamic energy dissipation of 12% of I c 0 for a rise/fall time of 1000 ps. It can be further reduced by reducing circuit inductances. Three stages of adiabatic QFP NOT gates were fabricated using a Nb Josephson integrated circuit process and their correct operation was confirmed.

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power consumption and very small switching energy. In this paper, we report a new AQFP cell library designed using the AIST 10 kA cm−2 Nb high-speed standard process (HSTP), which is a high-critical-current–density version of the AIST 2.5 kA cm−2 Nb standard process (STP2). Since the intrinsic damping of the Josephson junction (JJ) of HSTP is relatively strong, shunt resistors for JJs were removed and the energy efficiency improved significantly. Also, excitation transformers in the new cells were redesigned so that the cells can operate in a four-phase excitation mode. We described the detail of HSTP and the AQFP cell library designed using HSTP, and showed experimental results of cell test circuits.

We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells in the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.

SUMMARYWe describe the recent progress on a Nb nine-layer fabrication process for large-scale single flux quantum (SFQ) circuits. A device fabricated in this process is composed of an active layer including Josephson junctions (JJ) at the top, passive transmission line (PTL) layers in the middle, and a DC power layer at the bottom. We describe the process conditions and the fabrication equipment. We use both diagnostic chips and shift register (SR) chips to improve the fabrication process. The diagnostic chip was designed to evaluate the characteristics of basic elements such as junctions, contacts, resisters, and wiring, in addition to their defect evaluations. The SR chip was designed to evaluate defects depending on the size of the SFQ circuits. The results of a long-term evaluation of the diagnostic and SR chips showed that there was fairly good correlation between the defects of the diagnostic chips and yields of the SRs. We could obtain a yield of 100% for SRs including 70,000 JJs. These results show that considerable progress has been made in reducing the number of defects and improving reliability.

Genes in the FLOWERING LOCUS T (FT) family integrate external and internal signals to control various aspects of plant development. In soybean (Glycine max), FT2a and FT5a play a major role in floral induction, but their roles in post-flowering reproductive development remain undetermined. Ectopic overexpression analyses revealed that FT2a and FT5a similarly induced flowering, but FT5a was markedly more effective than FT2a for the post-flowering termination of stem growth. The down-regulation of Dt1, a soybean orthologue of Arabidopsis TERMINAL FLOWER1, in shoot apices in early growing stages of FT5a-overexpressing plants was concomitant with highly up-regulated expression of APETALA1 orthologues. The Dt2 gene, a repressor of Dt1, was up-regulated similarly by the overexpression of FT2a and FT5a, suggesting that it was not involved in the control of stem termination by FT5a. In addition to the previously reported interaction with FDL19, a homologue of the Arabidopsis bZIP protein FD, both FT2a and FT5a interacted with FDL12, but only FT5a interacted with FDL06. Our results suggest that FT2a and FT5a have different functions in the control of post-flowering stem growth. A specific interaction of FT5a with FDL06 may play a key role in determining post-flowering stem growth in soybean.

Adiabatic quantum-flux-parametron (AQFP) logic has the potential to operate with an ultimately small bit energy of several zeptojoules; however, this is too small to measure by conventional techniques. We measure such a small energy dissipation by coupling a superconducting resonator with an AQFP gate, where the insertion loss is sensitively varied with the small dissipation due to the very high Q factor of the resonator. We designed and implemented a 5 GHz superconducting resonator coupled with an AQFP gate. Measurement results show that the bit energy of the gate is ∼10 zJ at 5 GHz operation.

Reversible computing has been studied since Rolf Landauer advanced the argument that has come to be known as Landauer's principle. This principle states that there is no minimum energy dissipation for logic operations in reversible computing, because it is not accompanied by reductions in information entropy. However, until now, no practical reversible logic gates have been demonstrated. One of the problems is that reversible logic gates must be built by using extremely energy-efficient logic devices. Another difficulty is that reversible logic gates must be both logically and physically reversible. Here we propose the first practical reversible logic gate using adiabatic superconducting devices and experimentally demonstrate the logical and physical reversibility of the gate. Additionally, we estimate the energy dissipation of the gate, and discuss the minimum energy dissipation required for reversible logic operations. It is expected that the results of this study will enable reversible computing to move from the theoretical stage into practical usage.

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