No abstract

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power consumption and very small switching energy. In this paper, we report a new AQFP cell library designed using the AIST 10 kA cm−2 Nb high-speed standard process (HSTP), which is a high-critical-current–density version of the AIST 2.5 kA cm−2 Nb standard process (STP2). Since the intrinsic damping of the Josephson junction (JJ) of HSTP is relatively strong, shunt resistors for JJs were removed and the energy efficiency improved significantly. Also, excitation transformers in the new cells were redesigned so that the cells can operate in a four-phase excitation mode. We described the detail of HSTP and the AQFP cell library designed using HSTP, and showed experimental results of cell test circuits.

A new electrostatic tactile display is proposed to realize compact tactile display devices that can be incorporated with virtual reality systems. The tactile display of this study consists of a thin conductive film slider with stator electrodes that excite electrostatic forces. Users of the device experience tactile texture sensations by moving the slider with their fingers. The display operates by applying two-phase cyclic voltage patterns to the electrodes. The display is incorporated into a tactile telepresentation system to realize explorations of remote surface textures with real-time tactile feedback. In the system, a PVDF tactile sensor and a DSP controller automatically generate voltage patterns to present surface texture sensations through the tactile display. A sensor, in synchronization with finger motion on the tactile display, scans a texture sample and outputs information about the sample surface. The information is processed by a DSP and fed back to the tactile display in real time. The tactile telepresentation system was evaluated in texture discrimination tests and demonstrated a 79 percent correct answer ratio. A transparent electrostatic tactile display is also reported in which the tactile display is combined with an LCD to realize a visual-tactile integrated display system.

SUMMARYWe describe the recent progress on a Nb nine-layer fabrication process for large-scale single flux quantum (SFQ) circuits. A device fabricated in this process is composed of an active layer including Josephson junctions (JJ) at the top, passive transmission line (PTL) layers in the middle, and a DC power layer at the bottom. We describe the process conditions and the fabrication equipment. We use both diagnostic chips and shift register (SR) chips to improve the fabrication process. The diagnostic chip was designed to evaluate the characteristics of basic elements such as junctions, contacts, resisters, and wiring, in addition to their defect evaluations. The SR chip was designed to evaluate defects depending on the size of the SFQ circuits. The results of a long-term evaluation of the diagnostic and SR chips showed that there was fairly good correlation between the defects of the diagnostic chips and yields of the SRs. We could obtain a yield of 100% for SRs including 70,000 JJs. These results show that considerable progress has been made in reducing the number of defects and improving reliability.

No abstract

The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a J c = 2.5 kA cm −2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a J c = 10 kA cm −2 , nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a J c = 40 kA cm −2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.

No abstract

We designed a superconducting random access memory (RAM) in which all component circuits can be operated with dc-bias currents. A dc-powered superconducting loop driver and a dc-powered sense circuit are effectively combined with single flux quantum (SFQ) circuits. We proposed a pipeline structure for the memory cell array composed of the dc-powered loop drivers, the dc-powered sense circuits, passive transmission lines (PTLs), and SFQ gates. This pipeline structure enables a clock operation of 10 GHz even in a large-scale RAM. An effective device structure for the RAM based on a planarized multi-layer device structure was proposed. A dc-power layer and two PTL layers were placed under the ground plane. This structure is indispensable to create the pipeline structure using PTLs. The large inductance formed in the power layer enables low power dissipation of the RAM. We found from the estimations that 10 GHz clock operation with extremely low power dissipation can be achieved even in a large-scale RAM of 1 Mbit.