Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

Abstract

We designed a superconducting random access memory (RAM) in which all component circuits can be operated with dc-bias currents. A dc-powered superconducting loop driver and a dc-powered sense circuit are effectively combined with single flux quantum (SFQ) circuits. We proposed a pipeline structure for the memory cell array composed of the dc-powered loop drivers, the dc-powered sense circuits, passive transmission lines (PTLs), and SFQ gates. This pipeline structure enables a clock operation of 10 GHz even in a large-scale RAM. An effective device structure for the RAM based on a planarized multi-layer device structure was proposed. A dc-power layer and two PTL layers were placed under the ground plane. This structure is indispensable to create the pipeline structure using PTLs. The large inductance formed in the power layer enables low power dissipation of the RAM. We found from the estimations that 10 GHz clock operation with extremely low power dissipation can be achieved even in a large-scale RAM of 1 Mbit.

Memory states in small arrays of Josephson junctions

“…Since in currently available memory cell array designs memory cells are operated as separate (uncoupled) components with separate access to each cell, a seemingly straightforward route towards scalability would be following currently available designs (see, for example, references 6, 21, 22, 23). Moreover, since our proposed memory cell design seems to be much less complicated and lower size than, for example, today's state-of-the-art design [6] where Read and Write operations are implemented on separate circuits, peripheral circuits such as sense and current driver circuits could be also less complex and consequently lower size and perhaps requiring lower operational energy. We would also like to note that scaling memory cell to large arrays requires consideration of all the peripheral circuits (including decoders, drivers, sense circuits, and others [6,[21][22][23]).…”

“…A variety of designs has been proposed including memories based on single flux quantum digital logic [6], hybrid superconducting-CMOS designs [7,8], magnetic random access memory (RAMs) [9], and others [10]. Some of the main challenges in developing superconducting memory are reducing power dissipation, increasing access speed and reducing the size of the chip [10].…”

“…However, designing RAMs still poses significant challenges and the slow development of cryogenic memory is one of the major bottlenecks for advancement in cryogenic supercomputing. While SFQ technology provides seemingly satisfactory solutions for cryogenic processing, only 4096 bits of memory have been demonstrated so far [6]. Moreover, when projected to a 1 PB memory, the power dissipation nears 85 MW, which is unacceptable [10].…”

A random-access-memory cell based on quantum flux parametron with three control lines

“…There are several studies on large-scale memories using superconducting latching logic [11], partially using RSFQ logic [12], and fully using RSFQ logic up to date [13][14]. However, for the generous use of the advantage of the AQFP circuits, reduction of the energy consumption of the memories is essential.…”

“…For example, +50 A of current represents logic "1" and -50 A of current represents logic "0". Since the amplitude of control currents required for the memory cells in [11][12][13][14] is larger than 100 A, we have to develop a memory cell drivable by the AQFP signals.…”