Accurate inductance calculations are critical for the design of both digital and analogue
superconductive integrated circuits, and three-dimensional calculations are gaining
importance with the advent of inductive biasing, inductive coupling and sky plane shielding
for RSFQ cells. InductEx, an extraction programme based on the three-dimensional
calculation software FastHenry, was proposed earlier. InductEx uses segmentation
techniques designed to accurately model the geometries of superconductive integrated
circuit structures. Inductance extraction for complex multi-terminal three-dimensional
structures from current distributions calculated by FastHenry is discussed. Results for
both a reflection plane modelling an infinite ground plane and a finite segmented
ground plane that allows inductive elements to extend over holes in the ground
plane are shown. Several SQUIDs were designed for and fabricated with IPHT’s
1 kA cm − 2
RSFQ1D niobium process. These SQUIDs implement a number of loop structures that
span different layers, include vias, inductively coupled control lines and ground plane
holes. We measured the loop inductance of these SQUIDs and show how the
results are used to calibrate the layer parameters in InductEx and verify the
extraction accuracy. We also show that, with proper modelling, FastHenry can
be fast enough to be used for the extraction of typical RSFQ cell inductances.
We report the first experimental demonstration of recently proposed energy-efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic eliminating dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit operation. Two types of demonstration eSFQ circuits, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA/cm 2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.
At present, superconducting integrated circuit layouts are verified through a variety of techniques. A layout-versusschematic method implemented in Cadence allows extraction of circuit schematics with certain geometry-dependent parameters. Lmeter calculates inductance in a layout network and, with proper setup, may also calculate resistance separately. Recently, InductEx was introduced to calculate multiterminal network inductance in a superconductor structure with support for more complicated 3-D geometries. Here, we present an improvement to InductEx that allows resistance, inductance, and Josephson junction critical current extraction of a full superconducting digital logic gate or cell in a single execution, as well as in reasonable time. We show how InductEx was designed to operate on tape-out ready layouts and, through example, how it is used for full-gate layout verification of contemporary logic cells.
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