2009
DOI: 10.1007/978-90-481-3031-3_9
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A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]

Abstract: Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities and burgeoning die sizes in multi-core architectures. Partitioning a larger die into smaller segments and then stacking them in a 3D fashion can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible compared to intra-wafer distances. This attribute substantia… Show more

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