A self-tuning dvs processor using delay-error detection and correction

Das, Shidhartha; Pant, Sanjay; Roberts, David; Lee, Seokwoo; Blaauw, David; Austin, Todd; Mudge, Trevor; Flautner, Krisztián

doi:10.1109/vlsic.2005.1469380

Cited by 80 publications

(65 citation statements)

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“…Moreover, Razor also needs a minimum short path delay because when a clock is triggered, shadow latch at Razor will be waiting for a late coming signal, by means of a delayed clock, but at same time the short path results may change the shadow latch data, before critical path of previous clock discloses its data. Furthermore, there is a probability that metastability propagates through the error detection logic and causes metastability of the restore signal itself, which has been addressed in next versions by adding more circuitry like [39]. In [35] (which is an advanced form of [37]) a new FF is proposed that can handle both short and critical path errors and moreover the FF can recover critical path errors, like Razor, and also can predict short path errors.…”

Section: Discussionmentioning

confidence: 99%

Recent Subthreshold Design Techniques

Radfar

Shah²,

Singh³

2012

Active and Passive Electronic Components

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Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.

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Section: Discussionmentioning

confidence: 99%

Recent Subthreshold Design Techniques

Radfar

Shah²,

Singh³

2012

Active and Passive Electronic Components

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“…21,22 The most aggressive implementations of DVS were the Razor 23 and the Razor II. 24 They scaled power supply voltage until the part occasionally made errors which the system could correct.…”

Section: Run-time/design-time Adjustable Threshold Logicmentioning

confidence: 99%

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

Ghaffarishad

Mohammadzadeh

Ghaznavi‐Ghoushchi

2018

Circuit Theory & Apps

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The continued downscaling of CMOS technology has resulted in very high performance devices, but power dissipation is a limiting factor on this way. Power and performance of a device are dependent on process, temperature, and workload variation that makes it impossible to find a single power optimal design. As a result, adaptive power and performance adjustment techniques emerged as attractive methods to improve the effective power efficiency of a device in modern design approaches. Focusing on this issue, in this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. This method along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the workload requirement. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90-nm CMOS standard technology show that the proposed logic improves the average powerdelay product by about 40% for the attempted benchmarks. KEYWORDS adaptive voltage scaling (AVS), digital logic design, power-performance tunable logic, pseudodynamic logic | INTRODUCTIONIn the past few decades, digital circuit performance improved rapidly; mostly enabled by aggressive improvement of transistor performance. The exponential decrease in transistor feature sizes accompanied by exponential increase in transistor-switching speed has led to incredible computing power in today's integrated circuit. However, these devices have serious limitations on power dissipation. Obtaining energy efficiency and low peak power while maintaining computational performance is one of the primary goals in contemporary processor design.Transistor variability in very-large-scale integrated circuit. Increases with the very-large-scale integration process technology scaling trend, as smaller transistors have higher circuit parameter uncertainties. On the other hand, the off-leakage current of sub-100 nm processes is considerable. 1 In other words, in the sub-100 nm processes, the off-leakage power is a significant portion of the total power consumed by a circuit. For example, at the 90-nm technology node, leakage power may make up 42% of total power. 2 Beyond the circuit topology, the major factor in control and reduction of leakage power and current is the MOS transistors threshold voltage altering. Threshold voltage is subject of 2 different kinds of controllability: design-time and run-

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“…However, its efficiency is deteriorating because the performance difference between the replica and the actual critical path is significant due to increasing within-die variation. To more efficiently sense the timing margin, in-situ techniques have been studied [2]- [5]. However, this scheme inherently involves a critical risk of timing error occurrence.…”

Section: Introductionmentioning

confidence: 99%

“…"Razor I" in [2] and "Razor II" [3] rors with a delayed clock in a processor and correct the errors using extra recovery logic or re-execution of instructions. They control supply voltage monitoring the timing error rate and reduce power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction

Fuketa

Hashimoto

Mitsuyama

et al. 2009

IEICE Trans. Fundamentals

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Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90 nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters. key words: adaptive speed control, subthreshold circuit, timing error prediction, timing margin variability * Although a term "Canary Flip-Flop" is also defined in [6], its structure and purpose are different from canary FF referred in this paper. Canary FF in [6] is used to detect how much the supply voltage of FFs can be reduced without losing their states under DVS (Dynamic Voltage Scaling) systems.

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A self-tuning dvs processor using delay-error detection and correction

Cited by 80 publications

References 1 publication

Recent Subthreshold Design Techniques

Recent Subthreshold Design Techniques

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction

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