Recent Subthreshold Design Techniques

Abstract

Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.

Enhancing phonon flow through one-dimensional interfaces by impedance matching

“…Thermal management of devices at the nanoscale requires a comprehensive understanding of interfacial phonon transport. At length scales on the order of tens of nanometers, phonons flow quasi-ballistically and scattering at interfaces plays a dominant role on the overall thermal conductance [1][2][3][4][5]. Many applications stand to benefit from decreasing interfacial scattering; for instance, the heat generated in current transistors is blocked by their low thermal conductance [6,7], raising device temperature and impacting performance and reliability [8].…”

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

“…Transistor stacking [25] Off-state transistors connected in series cause significantly less leakage than a single device. Works in both active and standby mode Subthreshold logic [26][27][28] Utilizes subthreshold leakage current…”

Design & Analysis of Single Bit Sub-Threshold Sram Using Dtmos with Traditional Sram Design under 32nm Design

“…So the circuit stability can be improved [5][6][7][8][9]. Optimal characteristics & performance is obtained below the threshold region, with a supply voltage is less than the threshold voltage ,called sub threshold operation with a functional approach through read, write operations & Performance by power and delay is characterized A High Vth & low Vth transistor [6][7][8]are used to reduce the leakage power and Finally performance is estimated by static and dynamic power along with delay.…”