During the physical design process, the second process of the quantum circuit design°ow, using some optimization techniques after layout generation might be useful to improve the metrics or meet the design constraints. Focusing on this issue, this paper proposes an optimization technique using gate location changing to improve the latency of quantum circuits. The proposed technique uses layout and scheduling information to¯nd critical paths and improve their latency by changing locations of the gates on the critical paths. Experimental results show that the proposed technique decreases the latency of quantum circuits up to 26% for the attempted benchmarks.
Quantum circuit design flow consists of two main tasks: synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit objectives because of no information sharing between synthesis and physical design processes, we introduced the concept of "physical synthesis" for quantum circuit flow and proposed a technique for it. Following that concept, in this paper we propose a new technique for physical synthesis using auxiliary qubit selection to improve the latency of quantum circuits. Moreover, it will be shown that the auxiliary qubit selection technique can be seamlessly integrated into the previously introduced physical synthesis flow. Our experimental results show that the proposed technique decreases the average latency objective of quantum circuits by about 11% for the attempted benchmarks.
Recent works on quantum physical design have pushed the scheduling and placement of quantum circuit into their prominent positions. In this article, a mixed integer nonlinear programming model is proposed for the placement and scheduling of quantum circuits in such a way that latency is minimized. The proposed model determines locations of gates and the sequence of operations. The proposed model is proved reducible to a quadratic assignment problem which is a well-known NP-complete combinatorial optimization problem. Since it is impossible to find the optimal solution of this NP-complete problem for large quantum circuits within a reasonable amount of time, a metaheuristic solution method is developed for the proposed model. Some experiments are conducted to evaluate the performance of the developed solution approach. Experimental results show that the proposed approach improves average latency by about 24.09% for the attempted benchmarks.
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