Summary The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd.

In some quantum technologies, an interaction is only allowed between physically adjacent qubits, hence the nearest-neighbor requirement is needed. In such technologies, quantum gates are limited to operate on adjacent qubits. To make a quantum circuit compliant with the nearest-neighbor requirement, SWAP gates are inserted into the circuit to move the interacting qubits of a gate to be adjacent to each other. The mapping of qubits on the physical environment has an important role on reducing the number of SWAP gates and thus the circuit latency. Focusing on this issue, in this paper, a method is proposed that maps a quantum circuit onto a 3D physical hardware such as a 3D optical lattice. A new methodology for this mapping problem is proposed based on a complex network spectral clustering algorithm and graph theory, which are suitable for very large scale networks. It includes three steps: finding the order of qubit mapping, placing physical qubits, and routing. Simulation results show that the proposed mapping approach not only decreases the average number of SWAP gates by about 37% but also improves the average runtime by about 87% for the 2D architecture compared to PAQCS. Moreover, it reduces the average number of SWAP gates for the 3D architecture by 17.1% compared to the best studies in the literatures.