On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology

Roberts, David; Kim, Nam Sung; Mudge, Trevor

doi:10.1109/dsd.2007.4341526

Cited by 37 publications

(28 citation statements)

References 15 publications

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“…A similar idea was proposed independently in [19]. The salvage cache significantly improves on this by using a single nonfunctional block to repair several others.…”

Section: Related Workmentioning

confidence: 97%

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

Koh¹,

Wong

Chen³

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-There has been much work on the next generation of memory technologies such as MRAM, RRAM and PRAM. Most of these are non-volatile in nature, and compared to SRAM, they are often denser, just as fast, and have much lower energy consumption. Using 3-D stacking technology, it has been proposed that they can be used instead of SRAM in large level 2 caches prevalent in today's microprocessors. However, one of the key challenges in the use of these technologies, such as MRAM, is their higher fault probabilities arising from the larger process variation, defects in its fabrication, and the fact that the cache is much larger. This seriously affect yield. In this paper, we propose a fault resilient set associative cache architecture which we called the salvage cache. In the salvage cache, a faulty cache block is sacrificed and used to repair faults found in other blocks. We will describe in detail the architecture of the salvage cache as well as provide results of yield simulations that show that a much higher yield can be achieved viz-a-viz other fault tolerant techniques. We will also show the performance savings that arise from the use of a large next-generation L2 cache.

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“…A similar idea was proposed independently in [19]. The salvage cache significantly improves on this by using a single nonfunctional block to repair several others.…”

Section: Related Workmentioning

confidence: 97%

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

Koh¹,

Wong

Chen³

et al. 2009

2009 IEEE International Conference on Computer Design

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show abstract

“…Schemes such as Replication Cache [24] and ZerehCache [25] use external spare caches. Similarly, variants of fault-grouping and fault remapping have been used to tolerate faulty cache blocks without adding any spare elements, but by using other parts of the cache, such as GRP2 [26], RDC-Cache [27], Abella [28], Archipelago [29], and FFT-Cache [36]. Wilkerson's scheme [21] also could be considered to fall under this category.…”

Section: Architecture-level Techniquesmentioning

confidence: 99%

Multi-Layer Memory Resiliency

Dutt

Gupta

Nicolau

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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With memories continuing to dominate the area, power, cost and performance of a design, there is a critical need to provision reliable, high-performance memory bandwidth for emerging applications. Memories are susceptible to degradation and failures from a wide range of manufacturing, operational and environmental effects, requiring a multi-layer hardware/software approach that can tolerate, adapt and even opportunistically exploit such effects. The overall memory hierarchy is also highly vulnerable to the adverse effects of variability and operational stress. After reviewing the major memory degradation and failure modes, this paper describes the challenges for dependability across the memory hierarchy, and outlines research efforts to achieve multi-layer memory resilience using a hardware/software approach. Two specific exemplars are used to illustrate multilayer memory resilience: first we describe static and dynamic policies to achieve energy savings in caches using aggressive voltage scaling combined with disabling faulty blocks; and second we show how software characteristics can be exposed to the architecture in order to mitigate the aging of large register files in GPGPUs. These approaches can further benefit from semantic retention of application intent to enhance memory dependability across multiple abstraction levels, including applications, compilers, run-time systems, and hardware platforms.

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“…Bit-Fix method also adds three cycles of latency to the cache access time. Roberts et al [19] proposed a block grouping (pairing) scheme to form a new, fully working logical block. RDC-Cache [5] replicates a faulty word by another clean word in one way of the next cache bank in a chain of cache banks.…”

Section: Related Workmentioning

confidence: 99%

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs

BanaiyanMofrad

Homayoun

Kontorinis

et al. 2013

2013 International Green Computing Conference Proceedings

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On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology

Cited by 37 publications

References 15 publications

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

Multi-Layer Memory Resiliency

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs

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