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Abstract-MRAM has emerged as one of the most attractive non-volatile solutions due to fast read access, low leakage power, high bit density, and long endurance. However, the high power consumption of write operations remains a barrier to the commercial adoption of MRAM technology. This paper addresses this problem by introducing low-current probabilistic writes (LCPW), a technique that reduces write access energy by lowering the amplitude of the write current pulse. Although low current pulses no longer guarantee successful bit write operations, we propose and evaluate a simple technique to ensure correctness and achieve significant power reduction over a typical MRAM implementation.

Abstract-Modern microprocessor caches are often regarded as cool chip components that dissipate power uniformly. This research demonstrates that this uniformity is a misconception. Memory cell peripherals dissipates considerably higher power than the actual memory cell and this can result in up to 30 o C of temperature difference between the warmest and the coolest cache part. To be effective and accurate, cache temperature and power modeling and management must take this effect into account. We focus on the surrounding logic of the memory cell and apply two novel techniques, peripheral bit swapping (PBS) and peripheral monitor and shutdown (PMSD), to reduce the thermal variation and reduce the corresponding steady-state temperature and leakage power of the cache. Overall, our techniques, on average, decrease temperature by 8 o C for the L1 Data Cache and 5 o C for the shared L2 cache and reduce their thermal gradient by more than 75%, on average, and across SPEC2K benchmarks.I.

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