REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs

BanaiyanMofrad, Abbas; Homayoun, H.; Kontorinis, Vasileios; Tullsen, Dean M.; Dutt, Nikil

doi:10.1109/igcc.2013.6604500

Cited by 11 publications

(9 citation statements)

References 27 publications

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“…Recently, a variety of proposals have been introduced to meet the constraint of parametric failure rate in the NTV cache [27]- [34], [8], [9]. Compared with these technologies, the VANUCA has different features, such as immunity to dynamic MBUs, independence of accurate fault maps, and so on.…”

Section: G Comparison With the State-of-the-art Technologiesmentioning

confidence: 99%

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

Wang

Han

et al. 2016

IEEE Trans. VLSI Syst.

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In this paper, we investigate the feasibility of voltage adjustment in a large capacity cache, and propose the architecture of voltage-adaptable nonuniform cache access (VANUCA) that exploits near-threshold computing and multivoltage domain to approach the limit of V dd in a low-power cache. However, the adoption of near-threshold voltage (NTV) leads to a rocketing error probability in SRAM arrays, which has to be addressed by effective fault-tolerant techniques. Instead of using error correction code or data duplication, the VANUCA exploits the natural data redundancy across the whole memory hierarchy to enable fast fault recovery in the NTV cache. Based on the discovered data resilience and the multi-V dd architecture, the VANUCA is able to match vulnerable/invulnerable data clusters to available high-/low-voltage domains by utilizing the data migration mechanism in dynamic NUCA. The proposed VANUCA includes two important architectural techniques: 1) static assignment that assumes a fixed voltage domain partitioning and 2) DataMotion that dynamically fits the working set into heterogeneous cache banks through V dd switching. Experimental results show that the VANUCA achieves considerable improvements in energy efficiency over the conventional single-voltage domain NUCA cache.Index Terms-Cache design, fault tolerant, multi-V dd , near-threshold voltage (NTV), nonuniform cache access (NUCA).

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Section: G Comparison With the State-of-the-art Technologiesmentioning

confidence: 99%

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

Wang

Han

et al. 2016

IEEE Trans. VLSI Syst.

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“…Block disabling results in caches with variable associativity per set, determined by the number and distribution of faults in the cache. Tracking faulty cells at finer granularity, usually combined with a remapping mechanism, offers a great increase in the effective cache capacity, and some recent proposals exploit this observation with complex mechanisms [4], [5], [15]. In this paper we focus on the simpler block disabling for shared LLCs, and we leverage cache coherence to track and manage disabled blocks in private caches.…”

Section: Impact Of Variability On Large Caches At Ultra-low Voltmentioning

confidence: 99%

“…More complex mechanisms couple faulty entries using a remapping mechanism, which adds a level of indirection to the cache access, making more complicated the direct adoption of our techniques [4], [15].…”

Section: Related Workmentioning

confidence: 99%

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages

Ferrerón

Gracia

Alastruey-Benedé

et al. 2014

2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing

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Abstract-Power density has become the limiting factor in technology scaling as power budget restricts the amount of hardware that can be active at the same time. Reducing supply voltage to ultra-low voltage ranges close to the threshold region has the promise of great energy savings. However, the potential savings of voltage scaling are limited by the correct operation of SRAM cells, which is not guaranteed below Vdd min , the minimum voltage in which cache structures operate reliably.Understanding the effects of operating below Vdd min requires complex modeling, so we introduce an updated probability failure model of SRAM cells at 22nm and explore the reliability impact of lowering the chip voltage supply below Vdd min in sharedmemory coherent chip-multiprocessors (CMP) running a variety of parallel workloads. A microarchitectural technique to cope with cache reliability at ultra-low voltages is block disabling; however, in many cases, the savings in on-chip caches do not compensate for the consumption in the rest of the system, as the consumption increase of the off-chip memory may offset the on-chip gain.We make the case that existing coherence mechanisms can provide the substrate to improve energy savings with block disabling and propose two low-complexity techniques. Taking the best of both techniques we can scale voltage below Vdd min and reduce system energy up to 39%, and system energy-delay up to 10%. Besides, by lowering the CMP consumption in a powerconstrained scenario, we could activate offline cores, reaching a potential speedup between 3.7 and 4.4.

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“…The NSF Variability Expedition ( Figure 5) [49] seeks to build opportunistic computing systems where hardware variations are monitored and exposed to software layers (instead of being hidden behind pessimistic margins) enabling adaptations. The work has spanned circuit-level monitoring and test (e.g., [50], [51], [60]), variability emulation ( [52], [53]), runtime for embedded systems (e.g., [54], [55]), GPUs (e.g., [56], [48]), processors (e.g., [56], [58]), memories (e.g., [55], [64], [59]) and storage (e.g., [61], [62]). In the following, we briefly describe some of the research on memory variability done under the Variability Expedition.…”

Section: Variability Expeditionmentioning

confidence: 99%

“…Zhou [30] minimizes area overhead through joint optimization of cell size, redundancy, and ECC; and Ndai [31] performs circuitarchitecture codesign for memory yield improvement. More recent architectural schemes for cache resilience address newer challenges for multi and many-core platforms, such as scalability [32][59], variation in fault behaviors [11], non-uniform memory access latency [59], limited shared redundancy [33], lowoverhead multi-VDD support [37], and high costs of uniform design [34][35].…”

Section: Architecture-level Techniquesmentioning

confidence: 99%

Multi-Layer Memory Resiliency

Dutt

Gupta

Nicolau

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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With memories continuing to dominate the area, power, cost and performance of a design, there is a critical need to provision reliable, high-performance memory bandwidth for emerging applications. Memories are susceptible to degradation and failures from a wide range of manufacturing, operational and environmental effects, requiring a multi-layer hardware/software approach that can tolerate, adapt and even opportunistically exploit such effects. The overall memory hierarchy is also highly vulnerable to the adverse effects of variability and operational stress. After reviewing the major memory degradation and failure modes, this paper describes the challenges for dependability across the memory hierarchy, and outlines research efforts to achieve multi-layer memory resilience using a hardware/software approach. Two specific exemplars are used to illustrate multilayer memory resilience: first we describe static and dynamic policies to achieve energy savings in caches using aggressive voltage scaling combined with disabling faulty blocks; and second we show how software characteristics can be exposed to the architecture in order to mitigate the aging of large register files in GPGPUs. These approaches can further benefit from semantic retention of application intent to enhance memory dependability across multiple abstraction levels, including applications, compilers, run-time systems, and hardware platforms.

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REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs

Cited by 11 publications

References 27 publications

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages

Multi-Layer Memory Resiliency

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