Multi-Layer Memory Resiliency

Abstract

With memories continuing to dominate the area, power, cost and performance of a design, there is a critical need to provision reliable, high-performance memory bandwidth for emerging applications. Memories are susceptible to degradation and failures from a wide range of manufacturing, operational and environmental effects, requiring a multi-layer hardware/software approach that can tolerate, adapt and even opportunistically exploit such effects. The overall memory hierarchy is also highly vulnerable to the adverse effects of variability and operational stress. After reviewing the major memory degradation and failure modes, this paper describes the challenges for dependability across the memory hierarchy, and outlines research efforts to achieve multi-layer memory resilience using a hardware/software approach. Two specific exemplars are used to illustrate multilayer memory resilience: first we describe static and dynamic policies to achieve energy savings in caches using aggressive voltage scaling combined with disabling faulty blocks; and second we show how software characteristics can be exposed to the architecture in order to mitigate the aging of large register files in GPGPUs. These approaches can further benefit from semantic retention of application intent to enhance memory dependability across multiple abstraction levels, including applications, compilers, run-time systems, and hardware platforms.

Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems

“…Cons include that this class generally requires system-specific solutions (although for ECC reusable concepts are typically applied). Literature examples on the aforementioned concepts include: the Algorithmic Noise Tolerance (ANT) [Hegde and Shanbhag 2001] on modules with reduced functionality, [Hamming 1950], [Dutt et al 2014] on ECC .…”

A cross-layer SER analysis in the presence of PVTA variations

“…Process, Voltage, Temperature, and Aging (PVTA) variation is one of the major dark sides of the technology scaling [19][20][21][22][23][24]. Due to the process variations [25,26] attributes of transistors (such as gate length, oxide thickness, diffusion depth, and V th variation mainly because of random dopant fluctuation) deviate from their nominal value.…”