A cross-layer SER analysis in the presence of PVTA variations

Cross-layer custom instruction selection to address PVTA variations and soft error

“…Voltage drop is mainly a result of supply current changes combined with nonzero resistance and inductance of the power delivery network that lead to IR − drop and di/dt, respectively [23,15]. Note that current fluctuations mainly occur due to fluctuations in resource utilization impacted by architectural and application events such as cache misses and power/clk gating events [23].…”

“…It should be noted that SER estimation is widely addressed in prior work [17,60,33,[61][62][63][64][65][66][67][68][69][70][71], however, to the best of our knowledge, only [72,15] consider the combined impacts of PVTA variations and the effects of workload on soft error.…”

“…8 [72,15]. The method is based on a Monte-Carlo approach to capture the effects of process variations and the energy distribution of the particles.…”

“…Two major dark sides of nanometer silicon nodes in terms of performance and reliability are process, voltage, temperature, and transistor aging (PVTA) variations and soft error [10][11][12][13][14][15][16][17]. Due to layoutdependent process variations, attributes of transistors (such as gate length, oxide thickness and diffusion depth) in the fabricated silicon devices may be different from their specifications [18][19][20][21][22].…”

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

“…However, this technique ignores the beneficial effect of BTI aging on the sub-threshold current reduction, as shown in [19]- [21]. Moreover, in [22], a cross-layer SER analysis considering the effect of PVTA variations have been performed.…”