Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

Rossi, Daniele; Tenentes, Vasileios; Reddy, S.M.; Al-Hashimi, Bashir M.; Brown, A.D.

doi:10.1109/tcad.2017.2729399

Cited by 12 publications

(4 citation statements)

References 41 publications

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“…This small increase in power dissipation can be managed through power-saving techniques, such as those found in refs. [17,18,[23][24][25], thus not prohibiting the adoption of DPCAM in multi-core systems.…”

Section: Authormentioning

confidence: 99%

New Content Addressable Memory Architecture for Multi-Core Applications

Abumwais,

Obaid

2024

Computer Memory and Data Storage

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The future of massively parallel computation appears promising due to the emergence of multi- and many-core computers. However, major progress is still needed in terms of the shared memory multi- and many-core systems, specifically in the shared cache memory architecture and interconnection network. When multiple cores try to access the same shared module in the shared cache memory, issues arise. Cache replacement methods and developments in cache architecture have been explored as solutions to this. This chapter introduces the Near-Far Access Replacement Algorithm (NFRA), a new hardware-based replacement technique, as well as a novel dedicated pipeline cache memory design for multi-core processors, known as dual-port content addressable memory (DPCAM). The experiments show that the access latency for write/read operations of a DPCAM is lower than that of a set-associative (SA) cache memory, with the latency of a write operation staying the same regardless of the size of the DPCAM. It is estimated that the power usage will be 7% greater than a SA cache memory of the same size.

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Section: Authormentioning

confidence: 99%

New Content Addressable Memory Architecture for Multi-Core Applications

Abumwais,

Obaid

2024

Computer Memory and Data Storage

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“…Since the increase in total power is small and acceptable it will not affect the adoption of DPCAM in multi-core systems. This slight increase in power dissipation is acceptable and can be improved using different algorithms of power-saving techniques [23,24,[29][30][31] which are mainly used to improve static and dynamic power dissipation. CAM memories are commonly used in different computing applications, mainly in various types of networks and inside CPUs.…”

Section: Estimation Of a Power Dissipationmentioning

confidence: 99%

Dual-Port Content Addressable Memory for Cache Memory Applications

Abumwais¹,

Amirjanov²,

Uyar³

et al. 2022

Computers, Materials &Amp; Continua

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Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM. However, an estimation of the power dissipation showed that DPCAM consumes about 7% greater than a set-associative cache memory of the same size. These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.

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“…Since by decreasing VDD there will be decrease in leakage current, and lower VDD will be used. In case of standby mode and higher supply voltage for reducing the SRAM leakage [22].…”

Section: Drowsy-cache Techniquementioning

confidence: 99%

Comprehensive Analysis of 7T SRAM Cell Architectures with 18nm FinFET for Low Power Bio-Medical Applications

Kumar

Tripathi

2021

Silicon

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The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM 2 , 6T SRAM is 1.079µM 2 and that of 8T SRAM is 1.28µM 2 all the results are simulated in cadence virtuoso using 18nm technology.

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Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

Cited by 12 publications

References 41 publications

New Content Addressable Memory Architecture for Multi-Core Applications

New Content Addressable Memory Architecture for Multi-Core Applications

Dual-Port Content Addressable Memory for Cache Memory Applications

Comprehensive Analysis of 7T SRAM Cell Architectures with 18nm FinFET for Low Power Bio-Medical Applications

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