Reducing peak power with a table-driven adaptive processor core

Kontorinis, Vasileios; Shayan, Amirali; Tullsen, Dean M.; Kumar, Rakesh

doi:10.1145/1669112.1669137

Cited by 44 publications

(29 citation statements)

References 31 publications

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“…Peak power dissipation is important for processor design since the thermal budget of processor, cooling cost, power supply cost and packaging cost depend on the processor's peak power dissipation [23]. We now repeat the search (for the preferred core modes) but with a limit on the power budget.…”

Section: Power Constrained Core Selectionmentioning

confidence: 99%

Exploring Heterogeneity within a Core for Improved Power Efficiency

Srinivasan

Kurella

Koren

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Asymmetric multi-core processors (AMPs) comprise cores with different sizes of micro-architectural resources yielding very different performance and energy characteristics. Since the computational demands of workloads vary from one task to the other, AMPs can often provide a higher power efficiency than symmetric multi-cores. Furthermore, as the computational demands of a task change during its course of execution, reassigning the task from one core to another, where it can run more efficiently, can further improve the overall power efficiency. However, too frequent re-assignments of tasks to cores may result in high overhead. To greatly reduce this overhead, we propose a morphable core architecture that can dynamically adapt its resource sizes, operating frequency and voltage to assume one of four possible core configurations. Such a morphable architecture allows more frequent task to core configuration re-assignments for a better match between the current needs of the task and the available resources. To make the online morphing decisions we have developed a runtime analysis scheme that uses hardware performance counters. Our results indicate that the proposed morphable architecture controlled by the runtime management scheme, can improve the throughput/Watt of applications by 31% over executing on a static out-of-order core while the previously proposed big/little morphable architecture achieves only a 17% improvement.

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Section: Power Constrained Core Selectionmentioning

confidence: 99%

Exploring Heterogeneity within a Core for Improved Power Efficiency

Srinivasan

Kurella

Koren

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

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“…While hardware-enforced power bounds cannot yet be applied to individual cores, Satori and Kumar's work shows demonstrated that control at this level of granularity allowed a larger number of cores to be placed on a processor [17]. Follow-on work explored hierarchical, tabledrivent and gradient-ascent techniques for power scheduling that mitigated power bound violations [18], [12].…”

Section: Related Workmentioning

confidence: 99%

Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound

Rountree

Ahn

Supinski

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

145

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Abstract-Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel's Sandy Bridge family of processors, researchers now have a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment and detail both the opportunities and potential pitfalls of using this technique to control processor power.As part of this evaluation we measure power and performance for single-processor instances of several of the NAS Parallel Benchmarks. Additionally, we focus on the behavior of a single benchmark, MG, under several different power bounds. We quantify the well-known manufacturing variation in processor power efficiency and show that, in the absence of a power bound, this variation has no correlation to performance. We then show that execution under a power bound translates this variation in efficiency into variation in performance.

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“…Server hardware also comprises of power management features that can be controlled by frequency/voltage scaling and proactive tuning methodologies [15]- [18]. Memory subsystem…”

Section: B Platform Telemetry Abstraction Modelmentioning

confidence: 99%

Dynamic energy allocation for coordinated optimization in enterprise workloads

Khanna

Doshi

et al. 2011

2011 International Conference on Energy Aware Computing

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Power optimization and power control are challenging issues for server computer systems. To obtain power optimization in an enterprise server, one needs to observe temporal behavior of workloads, and how they contribute to relative variations in power drawn by different server components. This depth of analysis helps to validate and quantify various energy/performance trends important for power modeling. In this paper we discuss an adaptive infrastructure to synthesize models that dynamically estimate the throughput and latency characteristics based on component level power distribution in a server. In this infrastructure, we capture telemetry data from a distributed set of physical and logical sensors in the system and use it to train models for various phases of the workload. Once trained, system power, throughput and latency models participate in an optimization heuristics that re-distribute the power to maximize the overall performance/watt of an enterprise server. We demonstrate modeling accuracy and improvement in energy efficiency due to coordinated power allocation among server components.

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Reducing peak power with a table-driven adaptive processor core

Cited by 44 publications

References 31 publications

Exploring Heterogeneity within a Core for Improved Power Efficiency

Exploring Heterogeneity within a Core for Improved Power Efficiency

Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound

Dynamic energy allocation for coordinated optimization in enterprise workloads

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