SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the ß ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124µm 2 half-cell) and full 8T (0.1998µm 2 ) cells to date.

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Double-gate FinFET devices with asymmetric and symmetric poly-silicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show IV,I-O.lV, with off-currents less than 100nA/um at Vgs= 0.

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