High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

Kedzierski, J.; Fried, D.; Nowak, E.; Kanarsky, T.; Rankin, Jed; Hanafi, H.I.; Natzle, W.; Boyd, D.; Zhang, Ying; Roy, Rahul; Newbury, J.; Yu, Christine; Yang, Qingyun; Saunders, P.; Willets, C.; Johnson, Arthur H.; Cole, Steven; Young, Ho; Carpenter, N.; Rakowski, D.; Rainey, B.A.; Cottrell, P.E.; Ieong, M.; Wong, H.-S. Philip

doi:10.1109/iedm.2001.979530

Cited by 50 publications

(67 citation statements)

References 5 publications

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“…As compared with (100) silicon surfaces, hole mobility is enhanced while electron mobility is degraded in (110) surfaces [63]. These trends are consistent with previous reports of FinFET dependence on crystal orientation [12]. These anisotropy effects become even more important in trigate [64] or gate-all-around devices [65].…”

Section: Double-gate Finfetsupporting

confidence: 81%

“…2 quantifies the benefits of DG and UTB devices in terms of inverter gate delay through simulation using realistic device structures based on ITRS specifications [2] for sub-50-nm gate length technology generations. Body thickness requirements for each gate length are derived from scaling rules presented in [12] for DG devices; for single-gate UTB devices, body thicknesses are assumed to be half this value. Mixed-mode device simulation [13] is employed using the energy balance model for carrier transport.…”

Section: Circuit Performance Enhancement Of Thin-body Mosfetsmentioning

confidence: 99%

“…A simpler, more manufacturable process similar to conventional SOI CMOS processes was then developed to create a quasi-planar FinFET structure ( Fig. 10) with significantly less gate-to-source/drain overlap capacitance [12], [52]- [55]. The FinFET uses a single-gate material deposited over a silicon fin to form perfectly aligned gates along the fin sidewalls.…”

Section: Double-gate Finfetmentioning

confidence: 99%

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Extremely scaled silicon nano-CMOS devices

Chang¹,

Choi

Ha³

et al. 2003

Proc. IEEE

214

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Section: Double-gate Finfetsupporting

confidence: 81%

Section: Circuit Performance Enhancement Of Thin-body Mosfetsmentioning

confidence: 99%

Section: Double-gate Finfetmentioning

confidence: 99%

See 1 more Smart Citation

Extremely scaled silicon nano-CMOS devices

Chang¹,

Choi

Ha³

et al. 2003

Proc. IEEE

214

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“…For example, [55,120]SOI wafers create a requirement for new types of ion implantation process equipment. [119,99,98]most SOI wafers are fabricated using an ion implantation step employing a high dose of oxygen (Ibis' SIMOXTM SOI wafer process) or hydrogen (SOITEC's SmartCutTM SOI wafer process).…”

Section: Soi Prospectsmentioning

confidence: 99%

Silicon on Insulator Technology Review

Singh¹,

Saxena²,

Rastogi³

2011

IJESET

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“…Different strengths can be obtained by using either different oxide thickness (asymmetric oxide) [17] or materials of different work-function (e.g. n+ poly and p+ poly) for the front and the back gate (asymmetric work-function) [15].…”

Section: Double Gate Soi Devicesmentioning

confidence: 99%

Double-gate SOI devices for low-power and high-performance applications

Roy

Mahmoodi

Mukhopadhyay

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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Abstract:Double-Gate (DG) IntroductionThe scaling of conventional bulk CMOS technology is facing great challenges due to increased leakage and process variations with scaling down of device dimensions. Channel engineering techniques such as retrograde well and halo implantation are introduced to improve scalability and performance of such devices ( Fig. 1(a)) [1,2]. However, the scalability of such a device structure is limited due to increased short channel effects [3]. This has motivated the need for nonclassical silicon devices to extend CMOS scaling beyond 45nm node ( Fig. 1(b-d)). Ultra thin body SOI FETs employ very thin silicon body to achieve better control of the channel by the gate, and hence, reduced leakage and short channel effects. Use of intrinsic or lightly doped body reduces threshold voltage (Vt) variations due to random dopant fluctuations [4] and enhances the mobility of careers in the channel region and therefore ON current. In these devices, there can be a weak common back gate that is shared as a common substrate among all the transistors. Such a process is referred to as Ground Plane SOI (GP-SOI) [31]. Better scalability can be achieved by introduction of a second gate at the other side of the body of each transistor resulting in a Double Gate (DG) SOI structure ( Fig. 1(c)). Due to excellent control of short channel effects, double-gate SOI devices have emerged as the device of choice for circuit design in sub-50nm regime [5]. Low subthreshold leakage and higher ON current in DG devices make them suitable for circuit design in sub-50nm regime [6][7]. There are a variety of device structures suitable for double gate technologies. One of the promising structures is FinFET ( Fig. 1(d)) [8]. Double gate devices with isolated gates (independent gates) are also being developed [9][10]. Independent gate option can be useful for low power and mixed signal applications [10][11][12][13][14]. Such developments at the device level provide opportunities for new ways of circuit design for low power and high performance. In this paper, we first review the device design options for the double gate device structures (Section 2). Then, we discuss the circuit design options using such devices for logic and memory applications (Section 3 and 4). Double Gate SOI DevicesA classification of DG devices and their implications on circuit design is illustrated in Fig. 2. There are two main device processes possible for DG devices ( Fig. 2 and 3), namely (a) symmetric device with same gate material (e.g. near-midgap metals) and oxide thickness for the front and the back gate [15][16] and (b) asymmetric device with different strengths for front and back gates. Different strengths can be obtained by using either different oxide thickness (asymmetric oxide) [17] or materials of different work-function (e.g. n+ poly and p+ poly) for the front and the back gate (asymmetric work-function) [15].Regardless of the underlying device process, DG devices can also be classified in terms of their structure (Fig. 2). Typicall...

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High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

Abstract: Double-gate FinFET devices with asymmetric and symmetric poly-silicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show IV,I-O.lV, with off-currents less than 100nA/um at Vgs= 0.

Cited by 50 publications

References 5 publications

Extremely scaled silicon nano-CMOS devices

Extremely scaled silicon nano-CMOS devices

Silicon on Insulator Technology Review

Double-gate SOI devices for low-power and high-performance applications

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