In this report, we present a top-down VHDL modeling technique which consists of two main mod eling levels: specification level and functional level. We modeled a RISC Processor (RP) in order to demonstrate the feasibility and effectiveness of this methodology. All models have been simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results show feasibility of the modeling strategy and provide performance measures of RP design features.
2.1Architecture RP is a 32-bit processor which contains a data memory, a program memory, an ALU, registers, and a controller, as shown in Figure 1. Its features include a Harvard architecture which permits simultaneous data and program memory accesses in each instruction cycle, a large register address space which allows fast register-to-register access for more operands, and special purpose registers which enhance array data transfer both to and from the data memory. The RP also provides a simple hardware mechanism for automatic loopback at the end of an inner loop based on loop length and loop count.The register space (RS) of RP contains 256 32-bit registers, divided into two blocks of 128 registers each. The first block, called data registers, consists of vector access registers (VARs), accumulators, and registers for temporary operand storage. The second RS block, called the interface registers, consists of less frequently used control and I/O registers.The memory space (MS) of RP contains internal and external memory. Internal memory includes program memory and data memory. In our model, external memory is restricted to data RAM, though it can be extended to include program memory as well. The internal data memory and the external data memory share the same address space, and they are accessed via the same address and data buses.The ALU performs arithmetic, logic, and bit-manipulation operations. It is supplied with two operands from RS and, depending on the instruction, the operands are directed to the adder-shifter or multiply-accumulate unit. The result of the operation is returned to RS.The controller generates signals to initiate transfer of data via the buses, control the operation of ALU, and store data into registers or memories, according to the instruction currently stored in the instruction register (IR) as well as the status word.The I/O features of RP include a serialreceiver/transmitter port (SRT interface), and an 8-bit parallel port (host interface). The host interface consists of a 32-wordx8-bit circular buffer. The circular buffer can be simultaneously accessed by RP and the host device.