RT level power analysis

Zhu, Jianwen; Agrawal, Pankaj; Gajski, D.D.

doi:10.1109/aspdac.1997.600323

Cited by 4 publications

(1 citation statement)

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“…The authors propose subbanking, bitline segmentation, and multiple line buffers in order to minimize the energy dissipated when accessing the memory array. A fast register-transfer level power-estimation methodology has been presented in [13]. The methodology accurately estimates the power consumption for both the controller and data path.…”

Section: Related Workmentioning

confidence: 99%

Performance and power effectiveness in embedded processors - customizable partitioned caches

Петров

Orailoğlu

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural features of modern embedded processors. The automated methodology for customizing the processor microarchitecture that we propose results in increased performance, reduced power consumption and improved determinism of critical system parts while the fixed design ensures processor standardization. The resulting improvements help to enlarge the significant role of embedded processors in modern hardware-software codesign techniques by leading to increased processor utilization and reduced hardware cost. A novel methodology for static analysis and a microarchitecturally field-reprogrammable implementation of a customizable cache controller that implements a partitioned cache structure is proposed. Partitioning the load/store instructions eliminates cache interference; hence, precise knowledge about the hit/miss behavior of the references within each partition becomes available, resulting in significant reduction in tag reads and comparisons. Moreover, eliminating cache interference naturally leads to a significant reduction in the miss rate. The paper presents an algorithm for defining cache partitions, hardware support for customizable cache partitions, and a set of experimental results. The experimental results indicate significant improvements in both power consumption and miss rate.

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Section: Related Workmentioning

confidence: 99%