What input-language is the best choice for high level synthesis (HLS)?

Gajski, D.D.; Austin, Todd; Svoboda, Steve

doi:10.1145/1837274.1837489

Cited by 13 publications

(8 citation statements)

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“…Of course, HLD and HLS can be used to design the IPs with custom flexibility that can be reused later, to align with the first design direction. Over 30 top semiconductor companies were already adopting HLS tools in 2010 [63], relying heavily on automated tool-chains to generate sythesizable hardware description code, in order to quickly and efficiently conduct design space exploration. In the remainder of this chapter, the options are discussed and a methodology, is proposed which fully exploits the benefits of functional reconfiguration theory.…”

Section: Methodology For Exploring Functional Reconfigurabilitymentioning

confidence: 99%

Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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Current trends in architectural design require high-performance, low-power, flexible architectures that can adapt quickly onto the ever shifting and evolving application landscape. Finding the best architecture matching these stringent constraints is further limited by a short time-to-market window, which severely limits design exploration options. This work tackles these problems by proposing a different view on architectural flexibility, which can be exploited to achieve high energy-efficiency and performance instead of being traded off, by exploiting the advantages of reconfigurable architectures. Starting from a theoretical view, a methodology is produced for exploration of two different approaches in achieving high energy efficiency with two different architectural concepts: an architecture perfectly tuned to the application; and a new reconfigurable layered architecture, which can adapt its structure to match the application.

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Section: Methodology For Exploring Functional Reconfigurabilitymentioning

confidence: 99%

Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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“…For uniquely linking a resource to a PE automatically, template signals or (template) register arrays are defined. Thus, pe<4>, will have input signals a<4>, b<4> and output register out [4]. Resources must be declared globally, since multiple OPERATIONs need access to them, without a hierarchy (e.g.…”

Section: ) Modeling Similar Resources and Topologymentioning

confidence: 99%

“…and 2) High-level modeling -Designers move to a higher abstraction level for designing SoC components. Over 30 top semiconductor companies were already adopting High Level Synthesis (HLS) tools in 2010 [4], relying heavily on automated toolchains to generate sythesizable hardware description code, in order to quickly and efficiently conduct design space exploration.…”

Section: Introductionmentioning

confidence: 99%

Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC

Rakossy

Aponte

Chattopadhyay

2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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High Level Synthesis (HLS) and design is gaining traction in commercial and academic circles, as an answer to increasing design complexity and short time-to-market. In this paper, we present a short survey on the HLS landscape and propose modeling concepts to extract and exploit the inherent flexibility for a commercially available high-level design tool, to explore ASIC and CGRA besides native ASIP support. Structural descriptions, representation, flexibility and limitations are discussed. Several case studies help highlight the advantages of the proposed methods, providing a solid framework to aid a broader and faster design space exploration.

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“…Además, en la actualidad también se cuenta con herramientas que facilitan el trabajo de describir hardware a partir lenguajes de alto nivel como C, C++, SystemC [4], Matlab [5] e incluso en el último tiempo Rust [6]. Éstas herramientas aceleran el proceso de desarrollo de sistemas digitales, pero no siempre garantizan resultados óptimos en término de área utilizada y rendimiento del sistema [7].…”

Section: Introductionunclassified

FlowHDL, lenguaje de programación visual para el diseño digital de lógica programable

Antonelli

Gayoso

2021

Elek.

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Dentro del diseño digital de lógica programable se cuenta con una gran cantidad de herramientas de software, sin embargo se observa que existe la necesidad de disponer de mayores facilidades para los usuarios de estos sistemas. Los principios necesarios de usabilidad pueden ser provistos por los lenguajes de programación visual. Por otro lado, para generar código VHDL o Verilog sintentizable en una FPGA a través de un sistema visual coherente, es necesario superar múltiples inconvenientes. En este trabajo se presenta una nueva herramienta visual para el diseño de circuitos electrónicos digitales.

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What input-language is the best choice for high level synthesis (HLS)?

Cited by 13 publications

References 0 publications

Modeling, analysis and exploration of layers: A 3D computing architecture

Modeling, analysis and exploration of layers: A 3D computing architecture

Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC

FlowHDL, lenguaje de programación visual para el diseño digital de lógica programable

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