Component selection in resource shared and pipelined DSP applications

Bakshi, Smita; Gajski, D.D.; Juan, Hsiao-Ping

doi:10.1109/eurdac.1996.558231

Cited by 7 publications

(2 citation statements)

References 7 publications

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“…An interesting approach to establish safety of un-trusted programs is presented in [25]. In this approach referred to as Proof Carrying Code, the code producer provides a proof along with the program.…”

Section: Static Analysis Of Binariesmentioning

confidence: 99%

“…[23] describes how components can be combined to fulfill requirements on minimal costs. Actual application areas of dynamic software architectures include dynamic resource selection for service composition in grid computing [24], or evaluation of faster components against cheaper ones in digital signal processing [25]. An industry pilot for dynamic software architectures is described and its benefits over a static approach are observed in [26].…”

Section: Related Workmentioning

confidence: 99%

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Distributed Computing and Internet Technology

2010

Lecture Notes in Computer Science

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egov.iist.unu.edu. In the tradition of the ICDCIT conference series, ICDCIT 2010 welcomed presentations of research ideas and results in theory, methodology and applications of distributed computing and Internet technology. In addition, the conference emphasized that research in this area can play an important role in building a foundation for the development of e-Society Applications (e-Applications) and at the same time, that e-Applications can provide the relevance and context for such research. Establishing a connection between foundational and applied research in distributed systems and Internet technology with software and services that enable e-Applications was a key feature of ICDCIT 2010.A total of 91 papers were submitted for ICDCIT 2010. , with four invited papers received. The current proceedings are divided into six corresponding sections:1. Section 1 -Invited Papers includes four papers. The paper "Transactional Memory Today" by Maurice Herlihy presents the author's perspective on the nature of the transactional memory mechanism and the problem it is expected to address. The paper "Maintaining Coherent Views over Dynamic Distributed Data" by Krithi Ramamritham presents a scalable technique for executing continuous queries over dynamic data while making sure that correct results are always presented to users. The paper "Malware: From Modelling to Practical Detection" by R.K. Shyamasundar, co-authored with Harshit Shah and N.V. Narendra Kumar, surveys a theory behind malware in order to identify the challenges behind its detection, and proposes a new approach to malware detection. The paper "Semantic Frameworks-Meanings in the Architecture" by Jim Davies, co-authored with Jeremy Gibbons, VI Preface explains how the use of semantic technologies and model-driven engineering can greatly reduce the cost of consistency and coordination in software development, in system integration and in continuous interactions with users.2. Section 2 -Networking comprises five papers. The paper "Fuzzy-Controlled Source-Initiated Multicasting (FSIM) in Ad Hoc Networks" by Anuradha Banerjee and Paramartha Dutta proposes an intelligent multicast routing scheme that takes into account estimated network evolution in terms of residual energy, link stability, position of receivers in the multicast tree, etc. The paper "On Optimal Space Tessellation with Deterministic Deployment for Coverage in Three-Dimensional Wireless Sensor Networks" by Manas Kumar Mishra and M. M. Gore identifies a model for optimal coverage in three-dimensional wireless sensor networks, with the best trade-off between performance and the number of nodes. The paper "Seamless Handoff between IEEE 802.11 and GPRS Networks" by Dhananjay Kotwal Maushumi Barooah and Sukumar Nandi proposes a new scheme that provides seamless mobility between GPRS and IEEE 802.11 (WiFi) networks. The paper "A proposes a new data-gathering scheme for remote wireless sensor networks that offers the best energy and delay performance compared with existing popular schemes. Organiza...

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Section: Static Analysis Of Binariesmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Distributed Computing and Internet Technology

2010

Lecture Notes in Computer Science

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Partitioning and pipelining for performance-constrained hardware/software systems

Bakshi¹,

Gajski

1999

IEEE Trans. VLSI Syst.

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In order to satisfy cost and performance requirements, digital signal processing and telecommunication systems, are generally implemented with a combination of di erent components, from custom-designed chips to o-the-shelf processors. These components vary in their area, performance, programmability and so on, and the system functionality is partitioned amongst the components to best utilize this tradeo. However, for performance critical designs, it is not su cient to only implement the critical sections as custom-designed high-performance hardware, but it is also necessary to pipeline the system at several levels of granularity. We present a design ow and an algorithm to rst allocate software and hardware components, and then partition and pipeline a throughput-constrained speci cation amongst the selected components. This is performed to best satisfy the throughput constraint at minimal hardware cost. Our ability to incorporate partitioning with pipelining at several levels of granularity, enables us to attain high throughput designs, and also distinguishes our work from previously proposed hardware/software partitioning algorithms.

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Estimation and consideration of interconnection delays during high-level synthesis

Hallberg

Peng²

Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204)

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Component selection in resource shared and pipelined DSP applications

Cited by 7 publications

References 7 publications

Distributed Computing and Internet Technology

Distributed Computing and Internet Technology

Partitioning and pipelining for performance-constrained hardware/software systems

Estimation and consideration of interconnection delays during high-level synthesis

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