Automatic generation of bus functional models fromtransaction level models

Shin, Doh Chull; Abdi, Samar; Gajski, D.D.

doi:10.1109/aspdac.2004.1337694

Cited by 4 publications

(5 citation statements)

References 6 publications

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“…This is implemented as a SystemC module which interacts with the software. The abstract processor is modeled as a bus functional model, which allows operations onto the local bus, such as read and write operations [142].…”

Section: Hardware-software Interface At Transaction-accurate Architecmentioning

confidence: 99%

“…Deadlock,20,[37][38] 118,128,135,142,146, 176 Decomposition,15,[54][55] 113 Design space exploration,96-97, 99, 110-111, 136-139, 166-169, 181, 196-198, 209-210 spatial exploration, 96 temporal exploration, 96 Device drivers, 18, 69, 84-86, 88, 99, 153, 188 Differential pulse code demodulation (DPCD), 42-43, 111-112 Digital signal processor (DSP), 2, 50, 75-76 Direct memory access (DMA), 11-13, 34-37, E Embedded software, 6-7, 18, 56, 65, 85, 87, 119 Entropy encoder, 46, 115 Ethernet, 87, 188 Execution cycles, 143, 178, 179, 200-201, 203, 204 Execution model, 16-18, 20, 22-23, 25-26, 28, 48, 62, 106, 126, 134, 161-162, 164-166, 170, 180-181, 195-196, 199 Execution time, 13, 62, 65, 68, 95, 107, 112, 120, 136-137, 139, 142-143, 147, 149, 158, 167, 179, 184, 197, 205 F Field programmable gate array (FPGA), 73, 119, 202 Filter, 44-45, 47, 115 Finite state machine (FSM), 25, 119 First-In-First-Out (FIFO), 11, 16, 20, 32-33, 50, 60, 69, 88-89, 91-92, 109, 111, 113, 125, 130-135, 139, 141-142, 152, 154, 156-160, 168, 201 Flit, 37 Flynn, M., 72 Flynn's taxonomy, 72 Formal verification, 15 Frame, 38, 43-47, 65, 114-115, 117-119, 142, 146-147, 158, 170, 175-177, 197, 200, 203-205…”

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confidence: 99%

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Embedded Software Design and Programming of Multiprocessor System-on-Chip

Popovici

Rousseau

Jerraya

et al. 2010

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Section: Hardware-software Interface At Transaction-accurate Architecmentioning

confidence: 99%

mentioning

confidence: 99%

Embedded Software Design and Programming of Multiprocessor System-on-Chip

Popovici

Rousseau

Jerraya

et al. 2010

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“…The automatic interface synthesis is described in [2,26], and focuses on the automatic refinement of system level communication, which is based on channels through the bus functional model of the target architecture.…”

Section: Related Workmentioning

confidence: 99%

Platform designer: An approach for modeling multiprocessor platforms based on SystemC

Araujo

Gomes

Barros

et al. 2005

Des Autom Embed Syst

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This paper[3.5pc] presents the Platform Designer (PD) framework, a set of SystemC based tools that provide support for modeling, simulation and analysis of multiprocessor SoC platforms (MPSoC), at different abstraction levels. PD provides mechanisms for interconnection specification, process synchronization and communication, thus allowing the modeling of a complete platform, in a unified environment. To do that it uses an extension of the ArchC ADL and acsys, a tool that enables the automatic generation of a SystemC simulator of the platform. The main advantages of this approach are twofold. First, designers have more flexibility since they can integrate and configure different processors to the platform, using a single environment. Second, it enables a faster design space exploration, given that it automatically generates SystemC simulators of whole platforms at distinct abstraction levels. A number of platform variations can be tried out with minor design changes, thus reducing design time. Experimental results show the suitability of the platform simulator for design space exploration. Real applications (with medium complexity) run in the platform in few minutes. Combined with the facility to generate platforms with minor changes, this feature allows an improvement of the design space exploration.

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“…Existing research efforts divided SoC design phases into system level modeling, transaction level modeling and RTL (Register Transfer Level) modeling ( [3] [4] [5] [6]). In system level, the tasks are application requirement and constraint analysis, algorithm design.…”

Section: Introductionmentioning

confidence: 99%

Mapping Applications on Coarse-Grained Reconfigurable Systems Using Architecture Template Modeling

Wang

Cao

Yan

et al. 2007

2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics

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We introduce a novel architecture template modeling for mapping applications on coarse-grained reconfigurable SoC. System level design issues become critical with increasingly complex integrated circuits and time-to-market pressure continues relentlessly. Design reuse and early design decision for computation and communication are a "must". Our technique is based on a transaction level architecture template modeling methodology in which computation/communication co-design is performed with the architecture described in an abstract manner. Besides, we use eACOGA algorithm for hw/sw partition. eACOGA uses genetic algorithm to evolve the parameters of ant colony optimization, and makes use of such advantages as positive feedback and efficient convergence to search for optimal partition solutions. Experiments show our approach improves the quality and efficiency of hw/sw partition for reconfigurable SoC, and architecture template enhances system reuse of existing SoC design and achieves exploration speedup well.

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Automatic generation of bus functional models fromtransaction level models

Abstract: Abstract

Cited by 4 publications

References 6 publications

Embedded Software Design and Programming of Multiprocessor System-on-Chip

Embedded Software Design and Programming of Multiprocessor System-on-Chip

Platform designer: An approach for modeling multiprocessor platforms based on SystemC

Mapping Applications on Coarse-Grained Reconfigurable Systems Using Architecture Template Modeling

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