Transaction level modeling: an overview

Cai, Lukai; Gajski, D.D.

doi:10.1109/codess.2003.1275250

Cited by 164 publications

(210 citation statements)

References 4 publications

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“…To achieve this, a MoP is extracted from the synthesis process which includes only the SW/HW components where the timing delay is critical. From the hardware abstraction point of view, we consider a Transaction Level Model (TLM) [16] abstraction for the communication. This means that the application layer issues read/write transactions on the bus, abstracting from the communication protocol (see CAAM model [16]).…”

Section: Model Of Performance (Mop)mentioning

confidence: 99%

“…From the hardware abstraction point of view, we consider a Transaction Level Model (TLM) [16] abstraction for the communication. This means that the application layer issues read/write transactions on the bus, abstracting from the communication protocol (see CAAM model [16]). After synthesis, the following system components can be annotated with execution times/delays: the scheduler that implements the static order schedule within an SDFG and the hierarchical scheduling across different SDFGs, the actors, the tiles, the bus and the shared memories.…”

Section: Model Of Performance (Mop)mentioning

confidence: 99%

See 1 more Smart Citation

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

Fakih

Grüttner

Fränzle³

et al. 2013

IFIP Advances in Information and Communication Technology

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Abstract. The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task becomes even more challenging, because of shared processing, communication and memory resources. Model-checking techniques are capable of verifying the performance properties of applications running on these platforms. Unfortunately, these techniques are not scalable when analyzing systems with large number of tasks and processing units. In this paper, a modelchecking based approach that allows to guarantee timing bounds of multiple Synchronous Data Flow Applications (SDFA) running on shared-bus multicore architectures will be extended for a TDMA hypervisor architecture. We will improve the the number of SDFAs being analyzable by our model-checking approach by exploiting the temporal and spatial segregation properties of the TDMA architecture and demonstrate how this method can be applied.

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Section: Model Of Performance (Mop)mentioning

confidence: 99%

Section: Model Of Performance (Mop)mentioning

confidence: 99%

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

Fakih

Grüttner

Fränzle³

et al. 2013

IFIP Advances in Information and Communication Technology

View full text Add to dashboard Cite

show abstract

“…The number n of elements to be converted is given in the data memory at address 0. After clearing the register R [6] and R [2], n is loaded into register R [3]. Then, in the loop each single number is converted.…”

Section: Examplementioning

confidence: 99%

“…Here, the system description language SystemC is the de facto standard and was standardized by the IEEE [13]. Additionally to the inherent SystemC feature of specifying hardware and software in one language the concept of Transaction Level Modeling (TLM) [2] is supported by SystemC. TLM allows to describe the communication in a system in terms of abstract operations (transactions).…”

Section: Introductionmentioning

confidence: 99%

Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques

Große

Peraza

Klingauf

et al. 2008

Embedded Systems Specification and Design Languages

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The system description language SystemC enables to quickly create executable specifications at adequate levels of abstraction for both hardware/software integration and fast design space exploration. Besides the modeling of a system, verification has become a dominant factor in circuit and system design. Since SystemC is a versatile language based on C++, testbenches at different abstraction levels can easily be built. But the fault coverage of a manually developed testbench is hard to quantify. In this paper, an approach for measuring the quality of SystemC testbenches is presented. The approach is based on dedicated code coverage techniques and identifies all the parts of a SystemC model that have not been tested. Experimental results show the applicability of our methodology.

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“…The goal of the Transaction-Level Modeling (TLM) with SystemC [13] is to define a model where the details of the RTL bus communications are abstracted away either (1) instead of going through signal transitions, have a component directly call the method of another component, or (2) having the components communicating through buffered FIFO communications. In both cases abstract data types can also be used to bundle low-level bus data types into one chunk of data.…”

Section: Systemc Verificationmentioning

confidence: 99%

Reactivity in SystemC Transaction-Level Models

Doucet

Shyamasundar

Krüger

et al.

Hardware and Software: Verification and Testing

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Abstract. SystemC is a popular language used in modeling systemon-chip implementations. To support this task at a high level of abstraction, transaction-level modeling (TLM) libraries have been recently developped. While TLM libraries are useful, it is difficult to capture the reactive nature of certain transactions with the constructs currently available in the SystemC and TLM libraries. In this paper, we propose an approach to specify and verify reactive transactions in SystemC designs. Reactive transactions are different from TLM transactions in the sense that a transaction can be killed or reset. Our approach consists of: (1) a language to describe reactive transactions that can be translated to verification monitors, (2) an architectural pattern to implement reactive transactions, and (3) the verification support to verify that the design does not deadlock, allows only legal behaviors and is always responsive. We illustrate our approach through an example of a transactional memory system where a transaction can be killed or reset before its completion. We identify the architectural patterns for reactive transactions. Our results demonstrate the feasibility of our approach as well as support for a comprehensive verification using RuleBase/NuSMV tools.

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Transaction level modeling: an overview

Cited by 164 publications

References 4 publications

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques

Reactivity in SystemC Transaction-Level Models

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