The scalability of partially depleted (PD) SO1 with a floating body has been evaluated to below the sub-0.25ym regime using transistors, ring oscillators and 4 Mb SRAMs as test vehicles. In this piaper the speed and power performance of PD-SO1 are compared to those of bulk for 1.8V/sub-0.25pm logic applications. In addition, the 4Mb SO1 SRAM yield issues are revealid. Using the same transistor off-state leakage current limit criterion for both bulk and SOI, we conclude that PDSOI with a floating body will provide no speed and insignificant power advantage over bulk for sub-0.25pm logic applications.
We report a frequency-dependent output conductance of partially depleted SOI MOSFET's. For high-frequency analog applications, the output conductance is less than half and the dynamic range of V d is two times higher than the dc I I I-V V V characteristics would indicate. A simple physical model for the phenomenon that involves a phenomenological body charging capacitance and can fit data within 10% is presented.
By integrating the efforts in process, device and circuit simulations, this paper investigates the polysilicon-gate depletion effect (PDE) on performance of circuits composed of deep-submicron transistors. The tic and ac components of PDE on circuit performance are separated for the first time. The study delineates quantitatively the competing effect between the dc and ac PDE. Results of this study suggest the following: (i) PDE degrades circuit speed through dominance of the dc component in the competing effect. Reduction of gate oxide thickness lessens this dc PDE dominance behavior. (ii) Circuit speed degradation due to PDE becomes more significant during lowpower operation. (iii) The above phenomenon in (ii) can be substantially improved by thinning the gate oxide thickness.
IntroductionPolysilicon-gate depletion effect (PDE) [ 1-41 due to insufficient doping and insufficient activation of dopant near the polysilicon-Si0 interface becomes a major concern for MOS-FET performance degradation. It has adverse effect in transistor dc I-V characteristics by shifting device threshold voltage and reducing device current driving capability. Therefore, the dc component of the PDE degrades circuit speed performance. However, PDE also reduces transistor gate and overlap capacitances and it will speeds up the circuits. It is interesting to investigate the com'bined dc and ac effects of polysilicon-gate depletion on the performance of circuit composed of scaled-down sub-quarter micron device and operated at low power supply. In this paper, we have quantitatively studied the PDE competing dc and ac effects using integrated process, device and circuit simulations. The dc and ac components of PDE on circuit performance were separated for the first time. Their dependence on poly doping concentration and gate oxiide thickness was examined. PDE-induced circuit performance degradation under different power supply voltages was also studied.
Simulation ConditionsTransistor I-V and C-V data were generated from PISCES and SUPREM in this study. The polysilicon gate length and width are 0.15 pm and 10 pm respectively for both p-and nchannel non-LDD transistors. The overlap between the gate and draidsource is 0.02 pm per side. Substrate doping concentration (NXi ) is 8~1 0 '~ ~m -~. Doping concentration in polysilicon gate (Npooly) WiiS varied from 5~1 0 '~ to 5~1 0~' ~m -~. Oxide thickness (to,) was varied from lOOA down to 40A. The temperature (T) is 30C. In order to evaluate the circuit performance under the PDE, dc and ac transistor model parameters have been extracted for circuit simulation. BSIM2 dc transistor model [5,6] was used to extract transistor parameters from dc characteristics. A circuit-simulation model for PDE [7] was developed and used to extract the PDE parameters froim the ac characteristics of the transistors. This model has been verified by experimental CMOS ring oscillator data. Agreement between measurement and simulation is very good. The extracted PDE parameters coupled with the BSIMl ac transistor model [8] a...
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