An analytical model for self-limiting behavior of hot-carrier degradation in 0.25 mu m n-MOSFET's

Liang, Chunlin; Gaw, Henry T.; Cheng, Peng

doi:10.1109/55.192843

Cited by 36 publications

(7 citation statements)

References 5 publications

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“…In all cases, saturation occurs when mV. This saturated behavior has been attributed to a self-limiting effect, due to stress-induced defects (negatively charged during stress) that raise the energy barrier felt by hot electrons, pushing them away from the SiO -Si interface [23].…”

Section: B Gate-oxide Thicknessmentioning

confidence: 98%

Degradation Induced by X-Ray Irradiation and Channel Hot Carrier Stresses in 130-nm NMOSFETs With Enclosed Layout

Silvestri

Gerardin

Paccagnella

et al. 2008

IEEE Trans. Nucl. Sci.

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We present new experimental results about channel hot carrier degradation of enclosed layout transistors as a function of previous accumulated total ionizing dose, stress temperature, and transistor geometry. We show that the parametric degradation follows a power law, whose exponent is higher than in conventional open layout transistors, possibly due to a different diffusion geometry of hydrogen. Through physical simulation we attribute this effect to the electric field at the device corners, which leads to a non-uniform impact ionization. Previous irradiation reduces the channel hot carrier degradation in MOSFETs with 5.2-nm gate oxide, while having a minor influence with 2.2-nm gate dielectric.

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Section: B Gate-oxide Thicknessmentioning

confidence: 98%

Degradation Induced by X-Ray Irradiation and Channel Hot Carrier Stresses in 130-nm NMOSFETs With Enclosed Layout

Silvestri

Gerardin

Paccagnella

et al. 2008

IEEE Trans. Nucl. Sci.

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“…The time dependency functions for the device degradation, that follow from these models, consist of a power law for short stress times, while for long stress times different expressions for the time dependency of device degradation are used. In [9] it was proposed to use a logarithmic expression for the time dependency function of degradation for high stress times. In [10] an easily implementable, empirical expression was presented that combines these two stress regions.…”

Section: A Empirical Modelsmentioning

confidence: 99%

“…The main justification of this approach is, however, purely empirical [6] and only verified if the DC device degradation can be written as a power law function of time. From literature it is known that this power law may not always be applicable [7][8][9][10], and other time dependency functions for the device degradation are more appropriate. Justification for the quasi-static approach is lacking for such time dependency functions.…”

Section: Introductionmentioning

confidence: 99%

The hot carrier degradation rate under AC stress

Sasse

Bisschop

2010

2010 IEEE International Reliability Physics Symposium

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In this work the methodology used for predicting hot carrier device degradation under AC stressing conditions is critically re-examined. Having an accurate method is a key prerequisite of developing useful tools for the reliability simulation of any circuit. It will be shown that existing methods are not generally applicable. A new, better applicable method is presented and verified with experimental data.

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“…Since device lifetimes up to 10, 10 years are required in smartpower applications, accelerated stress tests and extrapolation approaches have been implemented in order to access device reliability in reasonable times [7][8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

“…Hu et al [7] proposed a model where the time-dependent hot-carrier degradation in MOSFETs follows a simple power-law, whereas in [8] it was shown that the degradation follows a logarithmic timedependence at longer times. In [9], the model by Goo [10] is enhanced by using a high-resolution measurement technique and non-linear least-square fit of the experimental degradation curves.…”

Section: Introductionmentioning

confidence: 99%

Hot-Carrier Degradation in Power LDMOS: Drain Bias Dependence and Lifetime Evaluation

Tallarico

Reggiani

Depetro

et al. 2018

IEEE Trans. Electron Devices

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In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power LDMOS transistors. When a relatively high drain voltage is applied during the on-state regime, high energetic and/or multiple cold electrons are recognized as the main source of degradation affecting the LDMOS lifetime: the latter is usually extrapolated at typical operating drain voltages. Hence, the extrapolation criterion is particularly critical and different models have been proposed in the past and discussed in this letter. In particular, the dependence of on-resistance degradation (ΔRON) on drain bias is investigated and a simplified extrapolation model, accounting for the saturation effects of the ΔRON at long stress times, is proposed and validated by comparison with experiments and advanced physics-based TCAD simulations, confirming the ability to accurately estimate lifetime on devices featuring short-circuited source-body contacts.

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An analytical model for self-limiting behavior of hot-carrier degradation in 0.25 mu m n-MOSFET's

Cited by 36 publications

References 5 publications

Degradation Induced by X-Ray Irradiation and Channel Hot Carrier Stresses in 130-nm NMOSFETs With Enclosed Layout

Degradation Induced by X-Ray Irradiation and Channel Hot Carrier Stresses in 130-nm NMOSFETs With Enclosed Layout

The hot carrier degradation rate under AC stress

Hot-Carrier Degradation in Power LDMOS: Drain Bias Dependence and Lifetime Evaluation

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