A study on the physical mechanism in the recovery of gate capacitance to C/sub ox/ in implanted polysilicon MOS structures

Lee, S.-W.; Liang, Chunlin; Pan, C.-S.; Lin, Wenhua; Mark, J.B.

doi:10.1109/55.144932

Cited by 33 publications

(9 citation statements)

References 5 publications

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“…Several reasons for unwanted frequency dispersions in SiO 2 have been investigated, such as surface roughness [14], polysilicon depletion [15,16,17], quantum confinement (only for an ultra-thin oxide layer) [18,19,20,21], parasitic effect (including series resistance, back contact imperfection and cables connection) [28,29,30], oxide tunneling leakage current (direct tunneling current, F-N tunneling etc .) [31], unwanted interfacial lossy layer [13] and dielectric constant ( k -value) dependence (dielectric relaxation) [26].…”

Section: Resultsmentioning

confidence: 99%

“…Several models and analytical formulae have been thoroughly investigated for correcting the data from measurement errors. Attention has been given to eliminate the effects of series resistance [12], oxide leakage, undesired thin lossy interfacial layer between oxide and semiconductor [13], surface roughness [14], polysilicon depletion [15,16,17] and quantum mechanical effect [18,19,20,21]. …”

Section: Introductionmentioning

confidence: 99%

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Extrinsic and Intrinsic Frequency Dispersion of High-k Materials in Capacitance-Voltage Measurements

et al. 2012

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In capacitance-voltage (C-V) measurements, frequency dispersion in high-k dielectrics is often observed. The frequency dependence of the dielectric constant (k-value), that is the intrinsic frequency dispersion, could not be assessed before suppressing the effects of extrinsic frequency dispersion, such as the effects of the lossy interfacial layer (between the high-k thin film and silicon substrate) and the parasitic effects. The effect of the lossy interfacial layer on frequency dispersion was investigated and modeled based on a dual frequency technique. The significance of parasitic effects (including series resistance and the back metal contact of the metal-oxide-semiconductor (MOS) capacitor) on frequency dispersion was also studied. The effect of surface roughness on frequency dispersion is also discussed. After taking extrinsic frequency dispersion into account, the relaxation behavior can be modeled using the Curie-von Schweidler (CS) law, the Kohlrausch-Williams-Watts (KWW) relationship and the Havriliak-Negami (HN) relationship. Dielectric relaxation mechanisms are also discussed.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Extrinsic and Intrinsic Frequency Dispersion of High-k Materials in Capacitance-Voltage Measurements

et al. 2012

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“…[3][4][5] In fact, the gate capacitance behavior with PIE and PAE is quite different that without PIE and PAE, which seriously re-shape the performance of a MOSFET varactor.…”

Section: Introductionmentioning

confidence: 93%

“…[1][2] As a result, a series of unique physics effects such as polysilicon accumulation (PAE), depletion (PDE) and inversion (PIE) related to this poly-silicon implant have also been experimentally observed. [3][4][5] Since the MOSFET operation may be in any point from the accumulation, thorough the depletion, to the inversion region, the poly-silicon accumulation as well as the inversion will definitely appear and affect device performance. In the past several years, the poly-silicon depletion effect has been extensively studied and a lot of theoretical models have been developed in the literature.…”

Section: Introductionmentioning

confidence: 99%

An Explicit Surface Potential Model of Bulk-MOSFETs with Inclusion of Poly-Gate Accumulation, Depletion, and Inversion Effects

Shi¹,

Song²,

Zhang³

et al. 2012

j comput theor nanosci

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An explicit surface potential model of the bulk-MOSFET with inclusion of the poly-gate accumulation, depletion, and inversion effects is derived from the basic MOS device physics and its solution result is also discussed in this paper. By the means of the appropriate approximations and device physics derivation, the complex group of the surface-potential and poly-silicon potential equations is transformed into one single explicit surface potential equation of a MOSFET with the poly-silicon accumulation/depletion/inversion effects. It is demonstrated that the proposed surface potential equation and its solution correctly yet accurately describe the physical behaviors of the poly-silicon potential, surface potential, gate charge, the gate capacitance, with continuous and smooth transitions from the accumulation region, thorough the depletion region, finally to the strong inversion region. The predicted MOSFET trans-capacitance behavior is verified by the result of fully numerical iteration method, thus, the surface potential equation presented can be used in advanced surface potential based MOSFET compact model development.

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“…This reduction was caused by gate polysilicon depletion layer formation, which manifests itself as an increase in the equivalent oxide thickness, leading to a reduction in MOSFET current drivability [5], [13]. Furthermore, a hump is observed in control oxide C-V curve in the deep inversion bias region due to the formation of an inversion layer near the polysilicon/SiO2 interface [14]. On the other hand, such dramatically distorted C-V curve is not observed in the NO-nitrided SOz, indicating that the boron penetration is suppressed.…”

mentioning

confidence: 99%

Highly suppressed boron penetration in NO-nitrided SiO/sub 2/ for p/sup +/-polysilicon gated MOS device applications

Han¹,

Wristers²,

Yan³

et al. 1995

IEEE Electron Device Lett.

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Absfruct-In this paper, we demonstrate the superior diffusion barrier properties of NO-nitrided SiOn in suppressing boron penetration for p+-polysilicon gated MOS devices. Boron penetration effects have been studied in terms of flatband voltage shift, decrease in inversion capacitance (due to polysilicon depletion effect), impact on interface state density, and chargeto-breakdown. Results show that NO-nitrided SiOz, as compared to conventional thermal SiOz, exhibit much higher resistance to boron penetration, and therefore, are very attractive for surface channel PMOS technology.N deep-submicrometer CMOS technology, p+-polysilicon I as the gate material for p-channel MOSFET is required to improve short-channel behavior [ 11, [2]. Unfortunately, boron diffusion from heavily doped p+-polysilicon through the thin gate oxide and into the underlying channel region can cause undesirable degradation of device operation, including instability in threshold voltage control, increase in charge trapping rate, decrease in low-field mobility [3], [4], and reduced current drivability due to polysilicon depletion in p-MOSFET's [5]. Previous studies have shown that "3-nitrided oxides and NZO-based oxides can suppress boron penetration [6]-[ IO]. However, "3-nitrided oxides suffer from hydrogen-related electron trapping problems [ 111 and NZO-based oxides require a much higher thermal budget for sufficient nitrogen concentration ([NI) to effectively suppress boron penetration 171. In this letter, we report the use of rapid thermal NO-nitrided Si02 as an alternate oxynitride with enhanced boron diffusion barrier properties while maintaining a low thermal budget and H-free nature of the processing ambient. The applicability of RTP NO-nitrided Si02 as gate dielectric in n+-poly gated MOSFET's has been recently demonstrated [12]. In this study, we examine the effects of boron penetration on flatband voltage (Vh), inversion capacitance (due to polysilicon depletion effect), interface state density (Dit), and charge-to-breakdown ( QBD) characteristics for p+-poly gated MOS devices. were fabricated on 10-15 0-cm, n-typeSi ( 100) substrates. All oxidation and nitridation processes were performed in a rapid thermal processing (RTP) system at 1 atm. Thermal oxides grown at 1050°C in pure 0 2 were used as control samples. Some samples then received in situ nitridation at 1000°C for 10 or 100 s in pure NO ambient. All samples finally received an in situ N2 anneal at 1050°Cfor 20 s. Undoped polysilicon with a thickness of 4000 8, was deposited by LPCVD at 625°C followed by BFz implants at 20 KeV with a dose of 5.5 x 1015 cm-'. Before the patterning of polysilicon, furnace N2 annealing for 30 min. at different temperatures (850, 900, and 950°C) was used to activate and redistributed the implanted boron. The final oxide thicknesses (measured by C-V) were -55 and -57A for control and the two NO-nitrided oxides, respectively.SIMS measurement (Fig. 1) reveals that the peak nitrogen concentration at the SiOz/Si interface for 1000°C/lOO s and 1000°C/...

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A study on the physical mechanism in the recovery of gate capacitance to C/sub ox/ in implanted polysilicon MOS structures

Cited by 33 publications

References 5 publications

Extrinsic and Intrinsic Frequency Dispersion of High-k Materials in Capacitance-Voltage Measurements

Extrinsic and Intrinsic Frequency Dispersion of High-k Materials in Capacitance-Voltage Measurements

An Explicit Surface Potential Model of Bulk-MOSFETs with Inclusion of Poly-Gate Accumulation, Depletion, and Inversion Effects

Highly suppressed boron penetration in NO-nitrided SiO/sub 2/ for p/sup +/-polysilicon gated MOS device applications

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