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Recently, it is often required in high performance analog IC design that some cells are placed symmetrically to horizontal or vertical axis. Balasa et al. proposed a method of obtaining the closest placement satisfying the given symmetry constraints and the topology constraints imposed by a sequence-pair, but this method has the following defects: (1) Some cells overlap each other. (2) The closest cell placement satisfying both the symmetry and topology constraints may not be obtained. (3) How to place cells symmetrically is mentioned only for one axis and there is no explanation for plural axes. In this paper, we propose an efficient method to obtain the closest cell placement satisfying the given symmetry constraints and the topology constraints imposed by a sequence-pair using linear programming. The proposed method obtains a simple constraint graph from a sequencepair and derives a set of linear constraint expressions from the graph. The number of linear expressions decreases by substituting the expressions for dependent variables. Then the solutions are obtained by linear programming. The effectiveness of the proposed method was shown by computational experiments.

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With being pushed into sub-16 nm regime, advanced technology nodes printing in optical micro-lithography relies heavily on aggressive Optical Proximity Correction (OPC) in the foreseeable future. Although acceptable pattern fidelity is utilized under process variations, mask design time and mask manufacturability form crucial parameters whose tackling in the OPC recipe is highly demanded by the industry. In this paper, we propose an intensity based OPC algorithm to find a highly manufacturable mask solution for a target pattern with acceptable pattern fidelity under process variations within a short computation time. This is achieved through utilizing a fast intensity estimation model in which intensity is numerically correlated with local mask density and kernel type to estimate the intensity in a short time and with acceptable estimation accuracy. This estimated intensity is used to guide feature shifting, alignment, and concatenation following linearly interpolated variational intensity error model to achieve high mask manufacturability with preserving acceptable pattern fidelity under process variations. Experimental results show the effectiveness of our proposed algorithm on the public benchmarks.

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Self-Aligned Double Patterning (SADP) has become one of the most promising processes for 20nm node technology and beyond. Despite its robustness against overlay, it is a challenging process for designers since predicting the wafer image instantly is almost impossible. Self-Aligned Quadruple Patterning (SAQP) is also critical technology for sub-10nm process but more complex than SADP, so it is too difficult to design a layout intuitively. Needless to say designing layout by applying N times sidewalls intuitively is impossible for almost everyone. In this paper, we clarify a new intuitive principle for SADP layout. The principle uses "Base patterns" painted in different two colors interchangeably. The proposed method enables us to design SADP layout simply by connecting and cutting fundamental pattern arbitrarily with a few restrictions. Another benefit is that either of two colors in the pattern can be used as mandrel. We can apply the principle to not only SAQP but also N times sidewall processes. Considering these advantages, layout formed by sidewall process becomes designer-friendly.