Improved method of cell placement with symmetry constraints for analog IC layout design

Abstract-In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a placement methodology that can handle all these constraints at the same time. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously. Experimental results do confirm the effectiveness and scalability of our approach in solving this mixed constraint-driven placement problem.

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“…It has been shown in [1] that a sufficient symmetry feasible condition [8] in a SP (s 1 , s 2 ) is the following.…”

Section: A Initial Scanmentioning

confidence: 99%

Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

Xiao

Tam

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…It is pointed out in [6] that condition (1) is sufficient but not necessary. More recently, the work of [3] presented another sequence-pair based approach for simultaneously satisfying symmetry and centroid constraints.…”

Section: Previous Work With Symmetry Constraintsmentioning

confidence: 99%

Regularity-constrained floorplanning for multi-core processors

Chen

2011

Proceedings of the 2011 International Symposium on Physical Design

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Multi-core technology becomes a new engine that drives performance growth for both microprocessors and embedded computing. This trend asks chip floorplanners to consider regularity constraint since identical processing/memory cores are preferred to form an array in layout. As chip core count keeps growing, manual floorplanning will be inefficient on the solution space exploration while conventional floorplanning algorithms do not address the regularity constraint. In this work, we investigate how to enforce regularity constraint in a simulated-annealing based floorplanner. We propose a simple and effective technique for encoding the regularity constraint in sequence-pairs. To the best of our knowledge, this is the first work on regularityconstrained floorplanning in the context of multi-core processor designs. Experimental comparison with a semi-automatic method shows that our approach yields an average of 22% less wirelength and mostly smaller area.

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“…Lin et al [11] also presented the symmetric-feasible conditions for the TCG-S representation. Two more recent works [9,14] further took advantage of the symmetryfeasible condition in sequence pairs [1]. Kouda et al [9] proposed a linear programming based method, and Tam et al [14] introduced a dummy node and additional constraint edges for each symmetry group after obtaining a symmetric-feasible sequence pair.…”

Section: Previous Workmentioning

confidence: 99%

“…Two more recent works [9,14] further took advantage of the symmetryfeasible condition in sequence pairs [1]. Kouda et al [9] proposed a linear programming based method, and Tam et al [14] introduced a dummy node and additional constraint edges for each symmetry group after obtaining a symmetric-feasible sequence pair. Most of the previous works showed that the symmetricfeasible conditions in the topological representations can handle the placement problem with a symmetry group effectively.…”

Section: Previous Workmentioning

confidence: 99%

Analog placement based on novel symmetry-island formulation

Lin

Lin²

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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In this paper, we present the first amortized linear-time packing algorithm for the placement with symmetry constraints. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible B*-trees (ASF-B*-trees) to directly model the placement of a symmetry island. Unlike the previous works that can handle only 1D symmetry constraints, our ASF-B*-tree is the first in the literature to additionally consider 2D symmetry. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and non-symmetry modules. Unlike the previous works, our approach can guarantee the close proximity of symmetry modules and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*-tree or an HB*-tree is the same as that for a plain B*-tree (only amortized linear) and much faster than previous works which need at least loglinear time. Experimental results show that our approach achieves the best published quality and runtime efficiency for analog placement.

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Improved method of cell placement with symmetry constraints for analog IC layout design

Cited by 22 publications

References 10 publications

Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

Regularity-constrained floorplanning for multi-core processors

Analog placement based on novel symmetry-island formulation

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