Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

Abstract

Abstract-In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a placement methodology that can handle all these constraints at the same time. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously. Experimental results do confirm the effectiveness and scalability of our approach in solving this mixed constraint-driven placement problem.

Slicing Floorplans with Handling Symmetry and General Placement Constraints

“…Apparently, there will be less difficulty if the problems of placement constraints and regularity are handled independently. Paper [3] successfully solved the problem of mixed constraints by SP and paper [6] improved the placement regularity by using it as part of the primary objective. However, if the two problems are treated by SP at the same time, the conflicts between various objectives will lead to the consumption of extra chip area.…”

“…Young et al [3] presented an approach to successfully solve the mixed constraint-driven placement problem with symmetry, common centroid and general constraints based on sequence pair (SP) [2]. In order to alleviate the congestion and improve the routability, some works [4], [6] introduced the regular structure to the non-slicing floorplan based on sequence pair and B*-trees [7] respectively.…”

Simultaneous analog placement and routing with current flow and current density considerations

“…However, most of the traditional analog layout synthesis algorithms address on either placement or routing individually [3,5,6,11,13,14,16,17,18,19,21,23,24]. As a result, placement is performed followed by routing, leading to an ordered synthesis flow.…”

Augmenting slicing trees for analog placement

“…Following the symmetric-feasible conditions or symmetryisland formulation, [3], [7], [8], [12], [15], [16], [23] tried to improve runtime and solution quality in terms of layout area by introducing more data structures and different algorithms. Balasa et al [3] imposed segment trees to improve the B*-tree packing time from O(n 2 ) to O(n lg n).…”

“…Krish et al [8] applied the priority queue to reduce the SP packing time from O(n 2 ) to O(m · n lg lg n). Koda et al [7] and Ma et al [12] integrated the linear programming (LP) and a graph structure, respectively, during SP packing to enhance the solution quality. Zhang et al [23] combined TCG and SP to shorten the TCG perturbation time.…”