Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control

Kodama, Chikaaki; Ichikawa, Hirotaka; Nakayama, Koichi; Kotani, Takayuki; Nojima, Shigeki; Motomizu, Shoji; Miyamoto, Shingo; Takahashi, Atsushi

doi:10.1109/aspdac.2013.6509607

Cited by 36 publications

(38 citation statements)

References 11 publications

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“…24,25 However, none of these works offered a pattern-centric design rule evaluation method, and this is the main contribution of our work. The rest of this paper is organized as follows.…”

Section: Prior Workmentioning

confidence: 99%

Layout pattern-driven design rule evaluation

Badr

Gupta

2014

SPIE Proceedings

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Abstract. With the use of subwavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as forbidden. These are the ones with a high yield impact or low routability impact, and these are to be prohibited in the design phase. The rest of the candidate bad patterns may be fixed in the postroute stage in a best-effort manner. The process developers need to optimize the process to be friendly to the patterns of high routability impact. Hence, an evaluation method is required early in the process to assess the impact of forbidding layout patterns on routability. We propose pattern-driven design rule evaluation (pattern-DRE), which can be used to evaluate the importance of patterns for the routability of the standard cells and, accordingly, select the set of bad patterns to forbid in the design. The framework can also be used to compare restrictive patterning technologies [e.g., litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), self-aligned octuple patterning (SAOP)]. Given a set of design rules and a set of forbidden patterns, pattern-DRE generates a set of virtual standard cells; then it finds the possible routing options for each cell without using any of the forbidden patterns. Finally, it reports the routability metrics. We present a few studies that illustrate the use cases of the framework. The first study compares LELE to SADP by using a set of forbidden patterns that are allowed by LELE but not by SADP. Another study compares LELE to extreme ultraviolet lithography from the routability aspect by prohibiting patterns that have LELE native conflicts. In addition, we present a study that investigates the effect of placing the active area of the transistors close to the P/N interface instead of close to the power rails.

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“…24,25 However, none of these works offered a pattern-centric design rule evaluation method, and this is the main contribution of our work. The rest of this paper is organized as follows.…”

Section: Prior Workmentioning

confidence: 99%

Layout pattern-driven design rule evaluation

Badr

Gupta

2014

SPIE Proceedings

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“…Triple patterning lithography (TPL) is one of the most promising techniques in the 14 nm logic node and beyond. In order to realize a target pattern, various types of techniques including design for manufacturability, such as LELE type double patterning lithograph [1][2][3][4][5][6][7], LELELE type TPL [8][9][10][11][12][13][14][15][16][17][18], LELECUT type TPL [19], and side wall process [20], are used in addition to a basic litho-etch process with optimized mask. These techniques are summarized in [21,22].…”

Section: Introductionmentioning

confidence: 99%

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography

Kohira

Matsui

Yokoyama

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently, LELECUT type TPL technology, where the third mask is used to cut the patterns, is discussed to alleviate native conflict and overlay problems in LELELE type TPL. In this paper, we formulate LELECUT mask assignment problem which maximizes the compliance to the lithography and apply a positive semidefinite relaxation. In our proposed method, the positive semidefinite relaxation is defined by extracting cut candidates from the layout, and a mask assignment is obtained from an optimum solution of the relaxation by randomized rounding technique.

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“…To date, manufacturing-friendly detailed routing studies follow the paradigms of sequential routing [11], [13], [28], [37], [45], [46] and negotiation-congestion-based routing technique [8], [9]. When a router accesses an I/O pin locally, it creates a routing interval pattern on M2 for the net connection as shown in Fig.…”

Section: Pin Access Planningmentioning

confidence: 99%

“…Reference [13] further improves the routing results by incorporating coloring scheme and layer assignment into a sequential router. Refereces [28], [29] focus on novel grid coloring techniques to guarantee SADP and SAQP friendliness during routing. Reference [9] proposes a novel graph model to capture the SADP-specific manufacturing constraints and delivers SADP-friendly routing results with negotiation-congestion-based routing scheme.…”

Section: Manufacturing-friendly Unidirectional Routingmentioning

confidence: 99%

“…Most existing manufacturing-friendly studies focus on the coloring scheme of routing patterns while leveraging SAMP-specific manufacturing constraints [8], [9], [11], [13], [28], [37], [45], c 2017 Information Processing Society of Japan [46], [57], [68]. Reference [45] presents the first SADP-aware detailed routing study by considering SADP-specific constraints during sequential routing procedure.…”

Section: Manufacturing-friendly Unidirectional Routingmentioning

confidence: 99%

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Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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Abstract:In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability. The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques. Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools. However, unidirectional layout style introduces significant impacts on the physical design flow. Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture. In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure. Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints. In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

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Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control

Cited by 36 publications

References 11 publications

Layout pattern-driven design rule evaluation

Layout pattern-driven design rule evaluation

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography

Toward Unidirectional Routing Closure in Advanced Technology Nodes

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