Layout pattern-driven design rule evaluation

Abstract

Abstract. With the use of subwavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as forbidden. These are the ones with a high yield impact or low routability impact, and these are to be prohibited in the design phase. The rest of the candidate bad patterns may be fixed in the postroute stage in a best-effort manner. The process developers need to optimize the process to be friendly to the patterns of high routability impact. Hence, an evaluation method is required early in the process to assess the impact of forbidding layout patterns on routability. We propose pattern-driven design rule evaluation (pattern-DRE), which can be used to evaluate the importance of patterns for the routability of the standard cells and, accordingly, select the set of bad patterns to forbid in the design. The framework can also be used to compare restrictive patterning technologies [e.g., litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), self-aligned octuple patterning (SAOP)]. Given a set of design rules and a set of forbidden patterns, pattern-DRE generates a set of virtual standard cells; then it finds the possible routing options for each cell without using any of the forbidden patterns. Finally, it reports the routability metrics. We present a few studies that illustrate the use cases of the framework. The first study compares LELE to SADP by using a set of forbidden patterns that are allowed by LELE but not by SADP. Another study compares LELE to extreme ultraviolet lithography from the routability aspect by prohibiting patterns that have LELE native conflicts. In addition, we present a study that investigates the effect of placing the active area of the transistors close to the P/N interface instead of close to the power rails.

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router

“…According to Constraint (1), e 1 1,2 , e 1 2,3 = 1, which connects between v1 and v3, since f 1 1,2 , f 1 2,3 are non-zero value. Constraint (1) forces e 2 1,2 , e 2 2,1 , e 1 2,1 to be zero so that the edge between v1 and v2 can be reserved only for n1.…”

“…Subsequently, [7] extend the DRE approach to chip-level analyses. Badr et al [2] suggest a pattern matching-based design rule evaluation method, which is then applied to checking of routing within standard cells. A fundamental distinction between these previous works and our present work is that we provide a new capability to assess design rule and patterning technology choices with cost-optimal detailed routing.…”

Road

“…Commodity Flow Conservation (CFC). Logical Expressions (3,4) represent the constraint of CFC, describing the commodity flow constraint on each vertex at a per-net and per-commodity granularity.…”

“…One of the major difficulties in the detailed routing is exposed by the resolution limitations coming from the diffraction limit of optical lithography which has 193nm (i.e., 193i) wavelength [11,12,23]. Although recent multi-patterning techniques [4,18,19] enable to deliver 10nm and sub-10nm technology nodes to foundries, they induce more complex conditional design rules for manufacturability which are new hurdles in the detailed routing procedure [2]. Routability becomes a critical bottleneck in detailed routing due to less number of routing tracks, higher pin density, and smaller pin geometry [23,25].…”

Layout pattern-driven design rule evaluation

“…(Foundries are encouraged to download the framework 31 and try it with their own patterns and rules). However, the applied forbidden patterns impose the restrictions of the patterning scheme that is used.…”