Layout pattern-driven design rule evaluation

Abstract

With the use of subwavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as forbidden. These are the ones with a high yield impact or low routability impact, and these are to be prohibited in the design phase. The rest of the candidate bad patterns may be fixed in the postroute stage in a best-effort manner. The process developers need to optimize the process to be friendly to the patterns of high routability impact. Hence, an evaluation method is required early in the process to assess the impact of forbidding layout patterns on routability. We propose pattern-driven design rule evaluation (pattern-DRE), which can be used to evaluate the importance of patterns for the routability of the standard cells and, accordingly, select the set of bad patterns to forbid in the design. The framework can also be used to compare restrictive patterning technologies [e.g., litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), self-aligned octuple patterning (SAOP)]. Given a set of design rules and a set of forbidden patterns, pattern-DRE generates a set of virtual standard cells; then it finds the possible routing options for each cell without using any of the forbidden patterns. Finally, it reports the routability metrics. We present a few studies that illustrate the use cases of the framework. The first study compares LELE to SADP by using a set of forbidden patterns that are allowed by LELE but not by SADP. Another study compares LELE to extreme ultraviolet lithography from the routability aspect by prohibiting patterns that have LELE native conflicts. In addition, we present a study that investigates the effect of placing the active area of the transistors close to the P/N interface instead of close to the power rails. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/15/2015 Terms of Use: http://spiedl.org/terms

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“…This is very useful in realising the three‐dimensional (3D) structure for FinFET devices. Owing to its larger set of design restrictions there have been several studies done to manage layout for SADP implementation [24–27]. The more emphasis on layout regularity may impact the total area and timing realisation for a certain layer.…”

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“…This is very useful in realizing the three dimensional structure for Fin-Shaped Field Effect Transistor devices. Owing to its larger set of design restrictions there have been several studies done to manage layout for SADP implementation [26][27][28][29]. The more emphasis on layout regularity may impact the total area and timing realization for a certain layer.…”