Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout

Koda, Shin-ichi; Kodama, Chikaaki; Fujiyoshi, Kunihiro

doi:10.1109/tcad.2007.891365

Cited by 23 publications

(16 citation statements)

References 10 publications

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“…In particular, the overall time complexity for packing an ASF-B * -tree or an HB * -tree is the same as that for a plain B * -tree (only linear) and much faster than previous works. Experimental results based on the MCNC benchmarks [15] and the real industry designs used in [16] show that our approach produces the best published results and runtime efficiency for analog placement. Furthermore, the scalability of our approach is much better than those of the previous works.…”

Section: B Our Contributionsmentioning

confidence: 98%

“…Lin et al [15] also presented the symmetric-feasible conditions for the TCG-S representation. Three more recent works [16]- [18] further took advantage of the symmetric-feasible condition in SPs [8]. Koda et al [16] proposed a linear-programming-based method, and Tam et al [17] introduced a dummy node and additional constraint edges for each symmetry group after obtaining a symmetric-feasible SP.…”

Section: A Previous Workmentioning

confidence: 99%

“…Three more recent works [16]- [18] further took advantage of the symmetric-feasible condition in SPs [8]. Koda et al [16] proposed a linear-programming-based method, and Tam et al [17] introduced a dummy node and additional constraint edges for each symmetry group after obtaining a symmetric-feasible SP. Krishnamoorthy et al [18] proposed an O(m · n lg lg n) packing-time algorithm by employing the priority queue, where m is the number of symmetry groups and n is the number of modules.…”

Section: A Previous Workmentioning

confidence: 99%

“…However, it is time-consuming to generate a relatively larger scale placement with several symmetry groups. For example, Koda et al [16] reported that it takes almost an hour on a 3.2-GHz Pentium PC to generate a symmetric placement of 110 modules with five symmetry groups.…”

Section: A Previous Workmentioning

confidence: 99%

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Analog Placement Based on Symmetry-Island Formulation

Lin

Chang

Lin³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B * -tree representation, we propose automatically symmetric-feasible (ASF) B * -trees to directly model the placement of a symmetry island. We then present hierarchical B * -trees (HB * -trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B * -tree or an HB * -tree is the same as that for a plain B * -tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement.

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Section: B Our Contributionsmentioning

confidence: 98%

Section: A Previous Workmentioning

confidence: 99%

Section: A Previous Workmentioning

confidence: 99%

Section: A Previous Workmentioning

confidence: 99%

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Analog Placement Based on Symmetry-Island Formulation

Lin

Chang

Lin³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Constraints for layout design and optimization [4][5][6][7][ [16][17][18][19][20][21][ [23][24][25][26][27][28][29][30][31][32][33][34][35][36] include the symmetry constraints for devices, direct current path branches, direct current paths, blocks and upper level circuits, the matching constraints for group of devices, the neighboring constraints, the protection constraints, the signal path and sequence constraints for direct current paths, and the direct current path and power reaching sequence constraints for group of devices. The symmetry constraints can be used for minimizing the mismatch by mirroring placement of devices, direct current path branches, direct current paths, blocks, or upper level circuits, and mirroring the wiring of interconnections to reduce the mismatch on devices and the mismatch on wires, in further to reduce mismatch on direct current path branches, direct current paths, blocks and upper level circuits during layout design and optimization, and such constraints can be gotten with encoding based symmetry direction.…”

Section: Layout Constraint Knowledgementioning

confidence: 99%